Github_Repos/cvw
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5,621 Commits 5 Branches 2 Tags 53 MiB
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172 Commits

Author SHA1 Message Date
Kevin Kim
ad63699aac fixed ctlzw bug in count unit 2023-02-18 20:12:30 -08:00
Kevin Kim
ecfcad20a0 zbb handles count instructions 2023-02-18 20:12:17 -08:00
Kevin Kim
543dc1e36a fixed bmuctrl decode bug 2023-02-18 20:11:50 -08:00
Kevin Kim
446327215d updated comments in bmuctrl 2023-02-18 19:57:10 -08:00
Kevin Kim
baff2c9362 rotate instructions now handled in ZBB unit 2023-02-18 19:56:54 -08:00
Kevin Kim
e4085764e7 removed redundant decode logic in bmuctrl 2023-02-18 19:50:36 -08:00
Kevin Kim
f18cd53dee began ZBB integration into ieu 2023-02-18 19:44:14 -08:00
Kevin Kim
5f56f72bb1 bmuctrl handles roriw 2023-02-18 16:26:16 -08:00
Kip Macsai-Goren
9c3aa55349 merge upstream synth changes 2023-02-18 14:35:19 -08:00
David Harris
92d4acf118 Removed unused PredInstrClassE register from bpred 2023-02-18 05:59:25 -08:00
David Harris
1af99c7aee Removed unused weq0M register fron fdivsqrtpostproc 2023-02-18 05:57:39 -08:00
David Harris
adc22235be Fixed issue #57 of sign selection for improperly NaN-boxed number 2023-02-18 05:34:40 -08:00
David Harris
7923d32c3a Fixed unpacking of illegal NaN box. Fixed issue #56 of sign injection NaN 2023-02-18 05:25:38 -08:00
Kevin Kim
2ccbde9d09 configured shifter in alu 2023-02-17 21:58:49 -08:00
Kevin Kim
f85c1058ff shifter bug fix 
- roli not passing unless I keep the MSB (instead of inverting) of truncated offset
 2023-02-17 21:58:26 -08:00
Kevin Kim
77fc40149f controller supports some rotates 2023-02-17 21:57:34 -08:00
Kevin Kim
5e7ed8804f bmuctrl supports some rotates 2023-02-17 21:57:19 -08:00
David Harris
63a6567ed3 Created PostBox signal to NaN-box malformed NaNs of excess length. Fixes Issue #55 2023-02-17 20:51:43 -08:00
Kevin Kim
9af0ffe3a9 added zero extend, pre-shift mux to ALU 2023-02-17 20:15:12 -08:00
Kevin Kim
cad0973b6b more elegant ZBA logic in controller 2023-02-17 20:14:47 -08:00
Kevin Kim
88d7c3b1f2 bmuctrl handles .uw instructions 2023-02-17 20:14:13 -08:00
David Harris
154d7eb9ef Fixed RAM bugs and refactored with read taking place after clock edge rather than before. 2023-02-17 19:14:38 -08:00
Kevin Kim
01f3cc2838 controller supports ZBA instructions 2023-02-17 16:44:16 -08:00
Kevin Kim
b09d942d60 removed Funct7 in Execute Stage 2023-02-17 16:12:09 -08:00
David Harris
daf2f822c2 Memory synthesis updates 2023-02-17 15:33:49 -08:00
David Harris
3f2f48ddc6 Continue fixing memory macros for synthesis 2023-02-17 15:15:37 -08:00
Ross Thompson
ae8b01b8d4 Renamed globalhistory predictor. 2023-02-17 16:08:34 -06:00
Ross Thompson
2661ec97d8 Fixed global history predictor. 2023-02-17 16:05:48 -06:00
Ross Thompson
a98a85f144 More updates. 2023-02-17 15:53:49 -06:00
Ross Thompson
1d9335c934 Updated global history predictor. 2023-02-17 15:53:15 -06:00
David Harris
aba29f6cc8 Synthesis with memories 2023-02-17 13:51:05 -08:00
Ross Thompson
e0a8974c7d Fixed a branch predictor performance issue. 2023-02-17 15:37:03 -06:00
Kevin Kim
a1570a88c9 bmuctrl checks for illegal zbs-style instructions 2023-02-17 12:54:08 -08:00
Kevin Kim
370ff54875 bctrl bug fix 
- bctrl decodes shift immediate instructions properly
 2023-02-17 11:16:29 -08:00
Kevin Kim
aba4eb80d4 alu bug fix 
- condmaskb piped in correctly instead of b
 2023-02-17 11:02:07 -08:00
Kevin Kim
07eaf146c2 alu looks at BSelect, added BSelect one hot signal 2023-02-17 09:51:49 -08:00
Ross Thompson
c97fa02300 Merge branch 'main' of github.com:ross144/cvw 2023-02-17 10:58:16 -06:00
Ross Thompson
3398c5156b Fixed bug with branch predictor. 2023-02-17 10:57:50 -06:00
Kevin Kim
323d14f9d9 added alu changes to previous commit 2023-02-17 08:22:13 -08:00
Kevin Kim
44c9612a5c added BSelect Signal 
- BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
 2023-02-17 08:21:55 -08:00
Kevin Kim
ada6023a41 comments 2023-02-17 07:53:14 -08:00
Kevin Kim
ab542a5bc3 comments 2023-02-17 07:52:54 -08:00
Kevin Kim
290fcd1789 comment formatting 2023-02-17 07:51:28 -08:00
Kevin Kim
5b341ac3a7 alu handles ALU select instead of funct3 2023-02-17 07:51:10 -08:00
Kevin Kim
ff365de54a added BMU controll 2023-02-17 07:50:59 -08:00
Kevin Kim
f0c81247e4 Added ALUSelect signal into datapath, ieu, controller 2023-02-17 07:50:45 -08:00
David Harris
0d2baed943 Reverted lab3 changes in dev branch 2023-02-16 18:10:05 -08:00
David Harris
26ea8b03c3 Merge branch 'lab3_2023' of https://github.com/openhwgroup/cvw into dev 2023-02-16 17:57:51 -08:00
David Harris
33eb5423cb Update datapath.sv 2023-02-16 17:53:31 -08:00
David Harris
113b124721 Update controller.sv 2023-02-16 17:52:44 -08:00
David Harris
43afa34338 Update alu.sv 2023-02-16 17:52:25 -08:00
Ross Thompson
b62bacbac3 keep this commit off of cvw. 2023-02-16 11:05:24 -06:00
David Harris
5b370bdc0f Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass. 2023-02-16 07:37:12 -08:00
Kevin Kim
921a32faf9 added comments to zbc units 2023-02-15 17:42:32 -08:00
Kevin Kim
50f0262498 zbc configurability and select mux 2023-02-15 17:39:37 -08:00
Kevin Kim
cd13913f07 controller forwards funct7 
- started the bmu controll register
 2023-02-15 17:38:12 -08:00
Kevin Kim
8feeaa5e94 zbc and carry-less multiply work properly 2023-02-15 17:37:09 -08:00
James Stine
a3aeff2703 Update if-then-else for ram items 2023-02-15 18:12:12 -06:00
Kevin Kim
2eb8721843 continued ZBC integration into ALU 2023-02-15 09:35:07 -08:00
Ross Thompson
c6920ab08e Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-15 11:29:39 -06:00
Kevin Kim
2a58a86371 added ALUResult Signal 2023-02-15 09:13:10 -08:00
Kevin Kim
27817c5b1d controller passes funct7 from decode to execute 2023-02-14 16:06:10 -08:00
Kevin Kim
857097282c git 2023-02-14 16:03:26 -08:00
Kevin Kim
420a0209dd Merge branch 'tmp' into main 2023-02-14 13:12:57 -08:00
Kevin Kim
7b7957594e removed unncessary stuff 2023-02-14 13:07:03 -08:00
Kevin Kim
1a209aac21 reverted back to I tests working 2023-02-14 13:06:31 -08:00
Kevin Kim
bcea347370 added ALU result select mux for B instructions 2023-02-13 17:38:00 -08:00
Kevin Kim
1364ac2a14 controller handles bclr 2023-02-13 16:57:05 -08:00
Ross Thompson
911023f441 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
fc3baa6846 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Kevin Kim
2679f06a00 Shadd instructions pass tests 2023-02-13 16:36:17 -08:00
Ross Thompson
f3c8c6e60a More fixeds to global history. 2023-02-13 18:08:51 -06:00
Ross Thompson
6ea830cf44 Fixed global history predictor. 2023-02-13 18:08:13 -06:00
Ross Thompson
3847d9e39a Updated global history predictor. 2023-02-13 18:07:32 -06:00
Ross Thompson
1ab2d0d19b Fixed bug in basic gshare implementation. Should be a better comparison to the speculative versions now. 2023-02-13 17:57:05 -06:00
Ross Thompson
c18ac35332 Created copy of gshare. I think there may be a simpler implementation. 2023-02-13 17:29:51 -06:00
Ross Thompson
10b45ed6c7 Further branch predictor improvements. 2023-02-13 17:23:56 -06:00
Ross Thompson
1cfdd201a5 Partial improvement. 2023-02-13 17:10:24 -06:00
Ross Thompson
0165fd54b4 Hacked commit. Fixes the gshare bugs introduced last week. 
Need to recover the good changes in the next commit.
 2023-02-13 16:14:17 -06:00
Kevin Kim
02a7dc45f0 ALU lint fixes 2023-02-13 14:01:51 -08:00
Kevin Kim
ed6a0466ad ALU configurability changes 
-stuff that was ZBA supported was in ZBB so I changed that
 2023-02-13 14:00:06 -08:00
Kevin Kim
c9e6b9aeef edited controller so that add.uw passes tests 2023-02-13 13:49:46 -08:00
Kevin Kim
cf09bbff5f alu add.uw needs w64 to be false 2023-02-13 13:49:35 -08:00
Ross Thompson
716fbca2b1 Partial fix for gshare bugs from the last two weeks. 2023-02-13 11:57:25 -06:00
Ross Thompson
51158e94ba Removed another bit from btb class. 2023-02-12 11:33:43 -06:00
Kevin Kim
19c8fa75f5 simulation runs-- clmul doesn't pass lint with xor tree 2023-02-11 21:22:33 -08:00
Kevin Kim
67db085b24 lint fixes 2023-02-11 21:13:10 -08:00
Kevin Kim
c7dbb49208 zbb, zbs, cnt lint fixes 2023-02-11 20:41:52 -08:00
Kevin Kim
016634d842 fixed byte unit lints 2023-02-11 20:25:34 -08:00
Kevin Kim
3653ea61b5 fixed lints in cnt 2023-02-11 20:22:42 -08:00
Kevin Kim
2dfbf15ff9 fixed typo in LZC 2023-02-11 19:59:03 -08:00
Kevin Kim
52ca8fa691 popcnt passes lint 2023-02-11 19:19:38 -08:00
Kevin Kim
2fefc3019e clmul passes lint 2023-02-11 19:16:13 -08:00
Ross Thompson
91fc883f6a More simplifications to the BP. 2023-02-10 17:09:35 -06:00
Ross Thompson
6fbca64eb7 Experimental branch prediction optimization. 2023-02-10 15:45:56 -06:00
Kip Macsai-Goren
f95038551f fixed small errors to get regression to run with bit manip supported. 2023-02-10 10:37:06 -08:00
Kip Macsai-Goren
137dd890a0 Merge remote-tracking branch 'upstream/main' into main 2023-02-10 10:01:14 -08:00
Ross Thompson
eafb406c9e Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-10 10:38:39 -06:00
Ross Thompson
ca0eb5a591 Modified branch predictor to use InstrValidE and InstrValidD rather than the more complex InstrClassE | WrongClassE logic. 2023-02-10 10:33:10 -06:00
Ross Thompson
91427ed72d RAS and RAS documentation now consistent. 2023-02-10 09:06:51 -06:00