David Harris
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1b0f878c16
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Renamed DivStartE to IFDivStartE
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2022-12-02 11:30:49 -08:00 |
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David Harris
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db5f3c15a4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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a86c9de36b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-02 04:28:50 -08:00 |
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David Harris
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6079a01bc8
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update test list
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2022-12-02 04:28:47 -08:00 |
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Ross Thompson
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602d191580
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 22:36:07 -06:00 |
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David Harris
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7c3e8553d1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 16:27:36 -08:00 |
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David Harris
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0d23ab3ec1
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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Ross Thompson
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3442b04f9e
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Properly flush cacheLRU.
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2022-12-01 17:32:58 -06:00 |
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David Harris
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3a8602523e
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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e403800ce8
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 11:47:54 -06:00 |
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Ross Thompson
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5025664cb0
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Removed unused port on cacheway.
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2022-12-01 11:47:48 -06:00 |
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David Harris
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28996d0b12
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-12-01 08:15:51 -08:00 |
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David Harris
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1bd639be6d
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code cleanup
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2022-12-01 08:15:48 -08:00 |
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Ross Thompson
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e6bd86f4fa
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 17:19:04 -06:00 |
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David Harris
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4ddc8fd603
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signal sufixes in integer division
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2022-11-30 15:15:37 -08:00 |
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Ross Thompson
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fa22484cfe
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Reverted the IROM/DTIM address range modelsim assignment.
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2022-11-30 17:13:33 -06:00 |
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Ross Thompson
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2f582cd91f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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a6355b1dcb
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More optimization.
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2022-11-30 11:26:48 -06:00 |
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Ross Thompson
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0aa7ce0b24
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Removed reset on dirty cache bits.
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2022-11-30 11:04:37 -06:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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10c2d45888
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Ross Thompson
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453ea36512
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Optimization of cacheway.
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2022-11-29 18:30:47 -06:00 |
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Ross Thompson
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fbf543bf57
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Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
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2022-11-29 17:19:31 -06:00 |
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Ross Thompson
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0277227323
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 14:57:38 -06:00 |
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Ross Thompson
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b5718c9baa
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Fixed a bug with the replacement policy. It was updating the wrong set on load hits.
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2022-11-29 14:51:09 -06:00 |
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Ross Thompson
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96cc4c7ebe
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Cleaned up the wavefile and added logic to linearly populate the LRU before all ways are filled.
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2022-11-29 14:09:48 -06:00 |
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Kip Macsai-Goren
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c7c578c104
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 10:43:44 -08:00 |
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Kip Macsai-Goren
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44ea8d8b22
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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Ross Thompson
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da82ab3712
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-29 11:52:35 -06:00 |
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Ross Thompson
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78acd40424
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Renamed signals in the cache.
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2022-11-29 10:52:40 -06:00 |
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Kip Macsai-Goren
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9b1765ce92
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added tests for invalid address being written to satp. Not passing regression
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2022-11-27 13:22:35 -08:00 |
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Ross Thompson
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6dd5668d21
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-22 18:07:32 -06:00 |
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cturek
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bdb9e24a66
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Almost done with Int division
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2022-11-22 22:22:59 +00:00 |
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cturek
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78c2ce5649
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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Ross Thompson
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279f5bc615
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Cleanup cacheLRU.
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2022-11-22 14:59:01 -06:00 |
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Ross Thompson
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e1dbe58632
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File name change for cachereplacement policy to cacheLRU
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2022-11-20 22:35:02 -06:00 |
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Ross Thompson
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4e926ba4cf
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Signal name changes for LRU.
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2022-11-20 22:31:36 -06:00 |
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Ross Thompson
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e99a424ddc
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Updated top level fpga file.
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2022-11-18 11:10:45 -06:00 |
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Ross Thompson
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d67ba9e55a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-17 17:45:59 -06:00 |
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Ross Thompson
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00218d559f
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Missing a file. Last commit will fail.
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2022-11-17 17:45:41 -06:00 |
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Ross Thompson
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47e1d1764b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-17 17:38:52 -06:00 |
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Ross Thompson
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0106777f02
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Finally have the correct replacement policy implementation.
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2022-11-17 17:36:37 -06:00 |
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Ross Thompson
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70d7fca750
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Updated fpga wave configuration.
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2022-11-16 15:57:19 -06:00 |
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Ross Thompson
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6ad9ba1e73
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 15:39:17 -06:00 |
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Ross Thompson
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faa13a96e0
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I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
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2022-11-16 15:38:37 -06:00 |
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Ross Thompson
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22ad49eef2
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Progress on the cache replacement policy implementation.
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2022-11-16 15:35:34 -06:00 |
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Ross Thompson
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847af7b95c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 12:44:06 -06:00 |
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Ross Thompson
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0796cd92fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-16 12:42:29 -06:00 |
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