Rose Thompson
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195def5808
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Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.
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2023-11-27 21:24:30 -06:00 |
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Rose Thompson
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beb95dd592
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Modified the pmachecker to correctly check the permissions for cmo instructions.
However this isn't fully tested.
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2023-11-27 17:44:11 -06:00 |
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Rose Thompson
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337903d8dd
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More cache simplifications.
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2023-11-27 14:59:42 -06:00 |
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David Harris
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1f57df7f8b
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Fixed reference to deleted atomic signal in cache
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2023-11-23 20:29:10 -08:00 |
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David Harris
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d3ce683e06
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Removed other unused signals from Verilog
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2023-11-20 23:37:56 -08:00 |
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David Harris
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f89fd8a7fe
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removed unused cache signals
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2023-11-20 23:16:35 -08:00 |
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David Harris
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acd8a63628
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Merge pull request #489 from ross144/main
fixes issue #487
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2023-11-18 19:22:33 -08:00 |
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Rose Thompson
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8cbd3de413
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Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.
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2023-11-18 19:01:39 -06:00 |
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David Harris
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eef39bd495
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Fixed typo in lsu parameter
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2023-11-15 08:30:48 -08:00 |
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David Harris
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817ddbc7c5
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Adjusted LSU misaligned buffer to fix synthesis warning
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2023-11-15 08:19:50 -08:00 |
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Rose Thompson
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a6995af91c
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Fixed bug in uncore updates which broke SDC.
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2023-11-13 16:15:23 -06:00 |
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Rose Thompson
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707b0c557c
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Cleanup and optimization of Zicclsm.
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2023-11-13 14:28:22 -06:00 |
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Rose Thompson
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cc7a0b211a
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Cleanup.
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2023-11-13 12:35:11 -06:00 |
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Rose Thompson
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c8cca8dfb8
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Simplification.
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2023-11-10 18:39:36 -06:00 |
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Rose Thompson
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c0e02ae190
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Found another bug in the RTL's Zicclsm alignment.
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2023-11-10 18:26:55 -06:00 |
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Rose Thompson
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02ab9fe99c
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Fixed all the bugs associated with the signature and the store side of misaligned access. Load misaligned is still causing some issues.
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2023-11-10 17:58:42 -06:00 |
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Rose Thompson
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84d86b1994
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Fixed spill bugs in the aligner.
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2023-11-10 17:18:45 -06:00 |
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Rose Thompson
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b74bfbeefd
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Merge branch 'main' into Zicclsm
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2023-11-10 16:15:32 -06:00 |
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Rose Thompson
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9abd26aad9
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Fixed bug which broke the non Zicclsm configs.
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2023-11-10 16:08:04 -06:00 |
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David Harris
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1f2899de14
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Modified rams to take USE_SRAM rather than P to facilitate synthesis
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2023-11-03 05:44:13 -07:00 |
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Rose Thompson
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0a4ed5515b
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Merge branch 'main' into Zicclsm
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2023-11-02 12:55:51 -05:00 |
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Rose Thompson
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13333d3e82
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Finally the d$ spill works. At least until the next bug. Definitely needs a lot of cleanup.
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2023-11-01 14:25:18 -05:00 |
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Rose Thompson
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5660eff57d
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Working through issues with the psill logic.
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2023-10-31 18:50:13 -05:00 |
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Rose Thompson
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f13b67b869
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Preemptively fixed the bytemask bug before testing.
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2023-10-30 15:47:46 -05:00 |
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Rose Thompson
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b5763e11e8
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rv32gc now also works with the alignment module. Still not tested with misligned access.
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2023-10-30 15:30:09 -05:00 |
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Rose Thompson
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9cd2e47783
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Aligner is integrated and enabled in rv64gc and passes the regression test; however, there are no new tests.
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2023-10-30 14:54:58 -05:00 |
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Rose Thompson
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569e3dc906
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Finally lints cleanly.
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2023-10-30 14:00:49 -05:00 |
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Rose Thompson
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dce3c85105
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Progress.
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2023-10-27 16:31:22 -05:00 |
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Rose Thompson
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747f453bb5
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Passes lint with some exceptions. Still need to add misaligned store support.
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2023-10-27 14:41:42 -05:00 |
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Rose Thompson
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36ca64c567
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At least have the aligner integrated, but not tested.
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2023-10-27 13:55:16 -05:00 |
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Rose Thompson
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657409aec5
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Addec ZICCLSM to config files and started on lsu instance.
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2023-10-27 13:07:23 -05:00 |
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Rose Thompson
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6041bf20b3
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The misaligned load alignment lints.
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2023-10-27 11:41:49 -05:00 |
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Rose Thompson
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834c0df697
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Added file.
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2023-10-27 09:49:44 -05:00 |
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Rose Thompson
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449abef823
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Progress on misaligned load/stores.
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2023-10-27 09:35:44 -05:00 |
|
Rose Thompson
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12763b7297
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begin implemenation of Zicclsm.
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2023-10-26 11:51:20 -05:00 |
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David Harris
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3bb7539429
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Fixed warnings of signed conversion and for Design Compiler
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2023-10-24 14:01:43 -07:00 |
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David Harris
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d526d28804
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Added MENVCFG.HADE bit and updated SVADU to depend on this bit
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2023-10-04 09:34:28 -07:00 |
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David Harris
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bd6eef2a51
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Initial implementation of SVNAPOT and SVPBMT does not break regression
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2023-08-25 18:33:08 -07:00 |
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Ross Thompson
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4eeba9bed9
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Added cbom test to custom. Needs to be moved to wally-riscv-arch-tests.
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2023-08-18 15:59:39 -05:00 |
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Ross Thompson
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0eac74ac7b
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Initial CMO implementation. Just adds control signals into the L1 caches.
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2023-08-14 15:43:12 -05:00 |
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Ross Thompson
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7a196d3fa7
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Cache cleanup.
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2023-07-31 14:12:53 -05:00 |
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Ross Thompson
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15dc76310e
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Fixed lint errors for issue #368. Does not fix simulation errors. We made a design decision a long time ago to not support DTIM on the rv32gc config because LLEN was greater than XLEN.
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2023-07-26 15:08:01 -05:00 |
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Ross Thompson
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f895898d22
|
Improved the critical path even more. The Arty A7 works upto 19Mhz easily. Testing out 22Mhz now.
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2023-07-21 16:31:26 -05:00 |
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Ross Thompson
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d04d2afed2
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Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
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2023-07-21 13:06:27 -05:00 |
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David Harris
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afe66d0ee4
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Added prefetch instructions; sent cbo instructions to LSU
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2023-07-02 10:55:35 -07:00 |
|
Ross Thompson
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85567841eb
|
Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
|
Ross Thompson
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009d8966e9
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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Ross Thompson
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b8a243827b
|
Found a whole bunch of files still using the old `define configurations.
|
2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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15928c5d7b
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Update swbytemask.sv
Program clean up
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2023-06-12 13:37:35 -07:00 |
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Harshini Srinath
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f3a7d9030c
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Update subwordwrite.sv
Program clean up
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2023-06-12 13:35:27 -07:00 |
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