Ross Thompson
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105763d938
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Fixed icache stalling cpu when doing an uncached operation.
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2022-01-03 23:49:19 -06:00 |
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Ross Thompson
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2d1cb0c3a3
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Reordered inputs/outputs in caches.
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2022-01-03 22:52:50 -06:00 |
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Ross Thompson
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ff24718c28
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Added generate around the spill logic so it is only used if supporting compressed instructions.
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2022-01-03 22:23:04 -06:00 |
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Ross Thompson
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120a9d6a58
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Minor improvement to icache.
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2022-01-03 22:00:35 -06:00 |
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Ross Thompson
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89f4b920ff
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More Icache clean up.
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2022-01-03 21:22:34 -06:00 |
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Ross Thompson
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2f7cb82c72
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Major icache cleanup.
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2022-01-03 21:12:17 -06:00 |
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Ross Thompson
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b045d84147
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Removed spill support from icache.
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2022-01-03 21:03:02 -06:00 |
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Ross Thompson
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8c7638688b
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The ifu now directly supports compressed without the icache providing the implemenation.
The icache still constains all the orignal muxing logic to handle spills. This should be removed.
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2022-01-03 20:49:47 -06:00 |
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Ross Thompson
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324362eee5
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Almost working compressed instructions with compressed detection and processing in ifu rather than icache.
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2022-01-03 18:10:15 -06:00 |
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Ross Thompson
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82fbc502e0
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Prepared the ifu and icache for moving spills to ifu.
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2022-01-03 17:09:36 -06:00 |
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Ross Thompson
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d77ddd2cbf
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Fixed bug with the icache.
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2022-01-03 15:55:19 -06:00 |
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Ross Thompson
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c501276067
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Fixed a bug where the instruction fetch got out of sync with the icache.
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2022-01-03 13:27:15 -06:00 |
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David Harris
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95407a6ea7
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Replaced && and || with & and | in non-fp files per new style guidelines
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2022-01-02 21:47:21 +00:00 |
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David Harris
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77c00e996b
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Started adding asynchronous TIMECLK for CLINT
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2022-01-02 21:18:16 +00:00 |
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Katherine Parry
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cf7aa4e8ae
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some errors in FP ArchTests fixed
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2022-01-01 23:50:23 +00:00 |
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David Harris
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25dd532b6a
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Removed .* from MMU.
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2021-12-31 07:19:51 +00:00 |
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David Harris
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272e884581
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Removed .* from CSRs
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2021-12-31 07:11:03 +00:00 |
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David Harris
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ae3767bd54
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-31 06:40:25 +00:00 |
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David Harris
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62e6aed7e5
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Simplified performance counters
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2021-12-31 06:40:21 +00:00 |
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Ross Thompson
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2096d45c23
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 18:10:36 -06:00 |
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Ross Thompson
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7055bfa4a7
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Added mux to select between uncache instruction requests and cached instructions requests.
Cacheless design almost works with the exception of compressed instructions.
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2021-12-30 18:09:37 -06:00 |
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Ross Thompson
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9432d9b72b
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Fixed wave.do.
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2021-12-30 17:57:07 -06:00 |
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Ross Thompson
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89dc598a83
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Patched up the linux-wave.do file.
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2021-12-30 17:53:43 -06:00 |
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David Harris
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19a47bd276
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 23:40:02 +00:00 |
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David Harris
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4066ea6463
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Fixes to counters; buildroot still broken
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2021-12-30 23:39:59 +00:00 |
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Ross Thompson
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2a2db23803
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Working without dcache.
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2021-12-30 16:01:31 -06:00 |
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Ross Thompson
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6942f20180
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 15:52:15 -06:00 |
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Ross Thompson
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89303579ee
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Progress on non dcache mode working.
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2021-12-30 15:51:07 -06:00 |
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David Harris
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adbcf835f8
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Moved SDC folder into uncore
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2021-12-30 21:38:24 +00:00 |
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Ross Thompson
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54d71006b1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 15:26:41 -06:00 |
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Ross Thompson
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fd77022f73
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No dcache now supported. Does not pass regression tests however.
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2021-12-30 15:26:32 -06:00 |
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David Harris
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ffc2a2097a
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Removed unnecessary generate inside hptw
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2021-12-30 21:21:00 +00:00 |
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David Harris
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25c634da8b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 21:15:00 +00:00 |
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David Harris
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700c3f8ca6
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Removed carry-save multiplier option from muldiv
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2021-12-30 21:14:57 +00:00 |
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Ross Thompson
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bd531d1996
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 14:56:24 -06:00 |
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Ross Thompson
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59a38e3efd
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Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu.
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2021-12-30 14:56:17 -06:00 |
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David Harris
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451f37729f
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Added names to generate blocks
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2021-12-30 20:55:48 +00:00 |
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Ross Thompson
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9ea308b2d7
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icache separated from bus fetch fsm. Does not work yet.
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2021-12-30 14:23:05 -06:00 |
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David Harris
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91b8d7d2eb
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 17:22:22 +00:00 |
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David Harris
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e084c8868f
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Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
|
2021-12-30 17:22:18 +00:00 |
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Ross Thompson
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f3fe91eba1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 11:01:22 -06:00 |
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Ross Thompson
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3803b9cd2d
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Changed names of Icache signals.
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2021-12-30 11:01:11 -06:00 |
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David Harris
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c1969ca142
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 16:49:36 +00:00 |
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David Harris
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da402f93cc
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Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run
|
2021-12-30 16:46:19 +00:00 |
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Ross Thompson
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26ad3fc11f
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Icache now works with any sized cache line a power of 2, greater than or equal to 32.
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2021-12-30 10:37:57 -06:00 |
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Ross Thompson
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8d5c86e908
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More name cleanup in caches.
|
2021-12-30 09:18:16 -06:00 |
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Ross Thompson
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e506957790
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Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
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2021-12-29 22:24:37 -06:00 |
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Ross Thompson
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e640f3f4fb
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-29 21:39:57 -06:00 |
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Ross Thompson
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903547f25f
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Removed WAdr from cacheway as it is redundant.
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2021-12-29 21:39:43 -06:00 |
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Ross Thompson
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525c7120b4
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Rename of dcache interface signals.
|
2021-12-29 21:26:15 -06:00 |
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