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226 Commits

Author SHA1 Message Date
David Harris
c0801263f1 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-23 20:43:22 -08:00
David Harris
bcc20c6bd5 Merge pull request #505 from stineje/main 
Update fix for cvtint testbench-fp
 2023-11-23 20:43:00 -08:00
David Harris
3df4c13daa Updated wallyTracer for Linux boot and wally-batch.do to remove buildroot checkpoint support 2023-11-23 20:36:45 -08:00
James E. Stine
1ab7522064 Update fix for cvtint testbench-fp 2023-11-23 17:56:51 -06:00
David Harris
d509644fa6 merged pr 2023-11-21 21:54:33 -08:00
David Harris
d1bb5c7512 Imperas fix for satp modes supported 2023-11-21 21:52:11 -08:00
Rose Thompson
8233ca999f Changed buildroot to run for 1M instructions only. 2023-11-21 23:46:45 -06:00
Rose Thompson
2767c8b410 Updated imperas.ic to support just sv48 and sv39. 2023-11-21 23:24:16 -06:00
David Harris
6bec559ba6 Removed stale signals from wave.do 2023-11-21 19:49:14 -08:00
Rose Thompson
e5b7301ffe Updated imperad dv vendor id and architecture id config. 2023-11-21 15:14:17 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
3594c08d4b Modified linux imperas tests to 
1. enable zicclsm
2. enable logging at 7000 ms
 2023-11-20 10:30:35 -06:00
David Harris
70c58a8ce1 Merge pull request #484 from ross144/main 
Changed bpred-sim.py to only simulate 12 jobs at once.
 2023-11-17 13:26:24 -08:00
Rose Thompson
8cf2c404bf bpred-sim only simulates 12 jobs at once. 2023-11-17 15:21:58 -06:00
David Harris
94201e993f Merge pull request #481 from ross144/main 
Fixed the BTB logger so sim_bp correctly reports BTB performance
 2023-11-15 17:45:38 -08:00
Rose Thompson
9a90c15f37 Extended SeparateBranch to support both just branches and all control flow instructions. 2023-11-15 16:36:49 -06:00
David Harris
cfaeeae25a Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter 2023-11-15 08:15:01 -08:00
Rose Thompson
feb45b9b59 Patched up linux imperas testbench. 2023-11-14 14:20:13 -06:00
Rose Thompson
fdb75203cb Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
Rose Thompson
95fc5f4a1c Towards removing the FPGA config file. 2023-11-13 17:20:26 -06:00
David Harris
426aabbc1a Imperas commenting 2023-11-10 08:26:32 -08:00
David Harris
7e00581187 Add Svadu support and SPI to imperas configuration 2023-11-10 06:27:25 -08:00
David Harris
625652b9ca Reporting stall path in synthesis script, support Zcb in Imperas 2023-11-09 06:59:29 -08:00
David Harris
2b183020d5 Fixed bit manpulation on imperas config 2023-11-06 14:11:01 -08:00
David Harris
9c4a7866b8 Fixed Svnapot_page_mask for imperas.ic 2023-11-05 06:51:01 -08:00
David Harris
568aa3c4a6 Verilator improvements 2023-11-04 03:21:07 -07:00
naichewa
fefb5adb8f code review harris 2023-10-31 12:27:41 -07:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
naichewa
2330f4ee63 hardware interlock 2023-10-30 17:00:20 -07:00
Rose Thompson
bd04ffc0c9 Fixed bug in bpred-sim.py for btb and class size sweep. 2023-10-24 10:29:02 -05:00
Rose Thompson
ea403e02ff Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction. 2023-10-23 16:09:40 -05:00
David Harris
b76c371e45 Config file cleanup 2023-10-18 05:38:36 -07:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
Rose Thompson
8f2ca2ae15 Added missing files. 2023-10-13 15:10:58 -05:00
eroom1966
d690708194 add in new .sv file 2023-10-06 13:47:05 +01:00
Lee Moore
0a0d6dd25e Merge branch 'openhwgroup:main' into main 2023-10-06 11:46:45 +01:00
Ross Thompson
3bbcfade93 Completed branch predictor benchmarking. 2023-09-27 13:56:51 -05:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
eroom1966
381cfdcb4b bring upto date with latest IDV 2023-09-21 11:29:31 +01:00
Ross Thompson
60ddbe31f8 Updated the branch predictor simulator's parseHPMC.py results. 
In a future commit I will update the branch predictor simulator with the fix for the gshare and then update the commit pointing their repo.
 2023-09-18 16:59:20 -05:00
Ross Thompson
95c653e7df Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way. 2023-09-15 14:05:26 -05:00
Ross Thompson
9ff3642c6c Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-09-05 11:12:00 -05:00
Ross Thompson
de54b5c4d8 Updated wavefile 2023-09-05 11:11:56 -05:00
David Harris
9747d122d2 tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
David Harris
1642ad2bad Improved NAPOT test coverage 2023-08-30 21:04:36 -07:00
Ross Thompson
310b700550 Have a working 32 bit cbom test! 2023-08-21 13:46:09 -05:00
Ross Thompson
a89a1e675c Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00