mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
merged pr
This commit is contained in:
David Harris
commit
d509644fa6
@ -49,7 +49,7 @@ configs = [
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)
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]
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def getBuildrootTC(boot):
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INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
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MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
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if boot:
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name="buildrootboot"
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@ -66,13 +66,6 @@ def getBuildrootTC(boot):
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BRgrepstr=str(INSTR_LIMIT)+" instructions"
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return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
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tc = TestCase(
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name="buildroot-checkpoint",
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variant="rv64gc",
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cmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot-checkpoint $RISCV 400100000 400000001 400000000\n!", # *** will this work with rv64gc rather than buildroot config?
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grepstr="400100000 instructions")
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configs.append(tc)
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tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
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tests64i = ["arch64i"]
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89
sim/wave.do
89
sim/wave.do
@ -4,13 +4,8 @@ quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate /testbench/FunctionName/FunctionName/FunctionAddr
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add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrIndex
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add wave -noupdate /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate /testbench/FunctionName/FunctionName/ProgramAddrMapLineCount
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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@ -74,7 +69,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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@ -353,42 +347,43 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
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add wave -noupdate -expand -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a1
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a2
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a3
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/we3
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add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
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add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
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add wave -noupdate -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MENVCFG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
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add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
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add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MISA_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MCAUSE_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
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add wave -noupdate -expand -group CSRs {/testbench/dut/core/priv/priv/csr/MSTATUS_REGW[21]}
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrm/MENVCFG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/SENVCFG_REGW
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add wave -noupdate -expand -group CSRs /testbench/dut/core/priv/priv/csr/csrs/csrs/STIMECMP_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FRM_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/FFLAGS_REGW
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add wave -noupdate -expand -group CSRs -group {user mode} /testbench/dut/core/priv/priv/csr/csru/csru/STATUS_FS
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
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@ -705,9 +700,13 @@ add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/STATUS_TW
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add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/PrivilegeModeW
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add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/wfi/WFICount
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add wave -noupdate -group wfi /testbench/dut/core/priv/priv/pmd/WFITimeoutM
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add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/Tag
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add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/TagWay
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add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelData}
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add wave -noupdate {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelWay}
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {39144 ns} 1} {{Cursor 4} {33684 ns} 1} {{Cursor 3} {39145 ns} 0}
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quietly wave cursor active 3
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WaveRestoreCursors {{Cursor 4} {39144 ns} 1} {{Cursor 4} {9705411 ns} 0} {{Cursor 3} {403021 ns} 1}
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quietly wave cursor active 2
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 194
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configure wave -justifyvalue left
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@ -722,4 +721,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {39053 ns} {39217 ns}
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WaveRestoreZoom {9705100 ns} {9705722 ns}
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