Ross Thompson
47638cdccf
Looks like rdtime was accidentally replaced with rrame from a find and replace.
2021-12-20 21:26:38 -06:00
David Harris
193885c958
Moved generate of conditional units to hart
2021-12-19 17:03:57 -08:00
David Harris
1196e5c191
Moved generate statements for optional units into wallypipelinedhart
2021-12-19 16:53:41 -08:00
Ross Thompson
7b2f5440a5
Changes to buildroot to support MemAdrM to IEUAdrM name changes.
2021-12-19 18:24:40 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
bbracker
6a6835ddc3
fix release of ReadDataM
2021-12-08 14:11:43 -08:00
bbracker
0c48725fa5
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
Skylar Litz
a69ab3bd1b
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
755c3e6a4c
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
bbracker
d90d708cf9
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Skylar Litz
e35faa9b8a
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
bbracker
23bd24323b
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Skylar Litz
99a15e7897
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
bbracker
24d3244cfe
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
3077769cbd
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
bbracker
e4cf044932
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
f39a509b5b
adapt testbench linux to use reset_ext
2021-10-25 13:26:44 -07:00
bbracker
c61cbf9618
change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
2021-10-25 12:25:32 -07:00
bbracker
b51e4d504b
some linux testbench cleanup
2021-10-25 10:04:30 -07:00
bbracker
eb9740bc31
manually resolved git merge conflicts in testbench linux after checkpointing
2021-10-24 15:02:19 -07:00
bbracker
dcd4d9dd9f
add checkpointing to linux testbench
2021-10-24 06:47:35 -07:00
bbracker
f6911be937
add W stage signals to linux testbench
2021-10-23 14:00:53 -07:00
bbracker
d6fb441666
add option for regression to do a partial execution of buildroot
2021-10-23 13:17:30 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
bbracker
5a987cf0ca
use correct string formatting function
2021-10-10 10:09:59 -07:00
bbracker
54e0e8eb5b
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
Skylar Litz
a924e79e26
added delayed MIP signal
2021-10-04 18:23:31 -04:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
bbracker
2ffdbdf6d2
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
Ross Thompson
6ac96db20b
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
0f87f68b9d
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
bbracker
441759b81c
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
b3f00f2682
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
a13b561759
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
b3849d8abb
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
...
InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
...
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
