80 Commits

Author	SHA1	Message	Date
Jarred Allen	6ce4d44ae1	Merge from branch 'main'	2021-04-08 17:19:34 -04:00
Thomas Fleming	e807f5d771	Implement support for superpages	2021-04-08 02:44:59 -04:00
Thomas Fleming	e04ad8f304	Fix extraneous page fault stall	2021-04-03 21:28:24 -04:00
Thomas Fleming	4b2765f8e2	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Jarred Allen	73d4dd8c15	Begin work on compressed instructions	2021-03-25 14:43:10 -04:00
Jarred Allen	fdecd6c56c	Clean up some stuff	2021-03-25 13:04:54 -04:00
Jarred Allen	e8e4e1bee2	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Thomas Fleming	89a2fe5741	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
bbracker	eea7e2e47e	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
bbracker	df51d9908d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
Thomas Fleming	062c4d40da	Connect tlb, pagetablewalker, and memory	2021-03-18 14:35:46 -04:00
David Harris	d4e84c58ed	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
David Harris	fe4d288589	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
Noah Boorstin	2d1f63b590	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
David Harris	52d4a04eb0	Created atomic test vector and directories	2021-03-08 09:38:55 -05:00
Thomas Fleming	e48dc38869	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
Thomas Fleming	692d4152fa	Begin hardware page table walker	2021-03-03 17:13:45 -05:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	225102047a	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	b121b90b28	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	74bc4c0444	Fixed lw by delaying read value by one cycle	2021-02-07 23:28:21 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00