Ross Thompson
b5d6c4fb46
Additional cleanup of ahblite.
2021-08-25 22:53:20 -05:00
Ross Thompson
bf312bb37c
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
David Harris
3783b5dc00
moved subwordread to lsu
2021-07-17 20:37:20 -04:00
David Harris
622a14cbdd
Removed more unused signals from ahblite
2021-07-17 02:21:54 -04:00
David Harris
52fcc47cdf
Removed rest of HRDATAW from ahblite
2021-07-17 02:15:24 -04:00
David Harris
1d171d7ea6
Commented out HRDATAW logic in ebu
2021-07-17 02:10:57 -04:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Ross Thompson
6041aef263
completed read miss branch through dcache fsm.
...
The challenge now is to connect to ahb and lsu.
2021-07-08 17:53:08 -05:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
David Harris
cc04009f82
Touched up TLB D and A bit checks
2021-07-04 18:17:09 -04:00
Ross Thompson
8e48865140
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-04 16:19:39 -05:00
Ross Thompson
9b959715a0
removed mmustall and finished port annotations on ptw and lsuArb.
2021-07-03 16:06:09 -05:00
David Harris
ee605d7550
Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
2021-07-03 03:29:33 -04:00
Ross Thompson
46831035fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-02 13:56:49 -05:00
Ross Thompson
2598f08782
Page table walker now walks the table.
...
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
bbracker
ced5039776
Revert "fixed forwarding"
...
This reverts commit 0f4a4a6ade
2021-06-24 17:39:37 -04:00
Ross Thompson
d8183e59e4
Works until pma checker breaks the simulation by reading HADDR rather than data physical address.
2021-06-24 14:42:59 -05:00
Ross Thompson
0377d3b2c9
Progress.
2021-06-24 13:05:22 -05:00
bbracker
0f4a4a6ade
fixed forwarding
2021-06-24 11:20:21 -04:00
Ross Thompson
6134c22aca
Split the ReadDataW bus into two parts in preparation for the data cache. On the AHB side it is now HRDATAW and on the CPU to data cache side it is ReadDataW. lsu.sv now handles the connection between the two.
...
Also reorganized the inputs and outputs of lsu and pagetablewalker into connects between CPU, pagetablewalker, and AHB.
Finally add DisableTranslation to TLB as teh pagetablewalker will need to force no translation when active regardless of the state of SATP.
With Kip.
2021-06-23 16:43:22 -05:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
David Harris
21a55458ca
Made MemPAdrM and related signals PA_BITS wide
2021-06-18 09:36:22 -04:00
David Harris
9dd3857c26
Fixed lint WIDTH errors
2021-06-09 20:58:20 -04:00
bbracker
17960a6484
Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
2021-06-08 12:41:25 -04:00
bbracker
5026a42fac
* GPIO comprehensive testing
...
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
2021-06-08 12:32:46 -04:00
Kip Macsai-Goren
7e41b17e65
restructured so that pma/pmp are a part of mmu
2021-06-04 17:05:07 -04:00
Thomas Fleming
980c00fa64
Clean up MMU code
2021-05-14 07:12:32 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
00c3b5a033
Remove remnants of InstrReadC
2021-05-03 17:36:25 -04:00
Thomas Fleming
94d734cca9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-05-03 14:02:19 -04:00
bbracker
9c08ce5359
rv32 plic test and lint fixes
2021-04-30 06:26:31 -04:00
Thomas Fleming
e091f430e0
Clean up PMA checker and begin PMP checker
2021-04-29 02:20:39 -04:00
Ross Thompson
44d28dbd1c
Icache integrated!
...
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
8d77012995
progress on bus and lrsc
2021-04-26 07:43:16 -04:00
Thomas Fleming
6f23858609
Fix HSIZE and HBURST signal widths in PMA checker
2021-04-23 20:11:43 -04:00
Ross Thompson
d7fea1ba3c
almost working icache.
2021-04-23 16:47:23 -05:00
Ross Thompson
c9bdaceddb
Fixed icache for 32 bit.
...
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Ross Thompson
04eb302925
Yes. The hack to not repeat the d memory operation fixed this issue.
2021-04-22 15:22:56 -05:00
Thomas Fleming
74fb1dccad
Prepare to squash bad ahb accesses
2021-04-22 15:36:45 -04:00
Thomas Fleming
e7822ce20c
Implement first pass at the PMA checker
2021-04-22 15:34:02 -04:00
Thomas Fleming
4d4ca24640
Extend stall on leaf page lookups
2021-04-22 01:51:38 -04:00
Thomas Fleming
70c801331a
Implement virtual memory protection
2021-04-21 19:58:36 -04:00
Jarred Allen
59b340dac9
Merge branch 'main' into cache
2021-04-19 00:05:23 -04:00
Noah Boorstin
d0a137ce0c
neat verilog thing
2021-04-18 17:48:51 -04:00
bbracker
195cead01c
working GPIO interrupt demo
2021-04-15 21:09:15 -04:00
Jarred Allen
757b64e487
Merge branch 'main' into cache
...
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
Thomas Fleming
bb2d433971
Fix mmu lint errors
2021-04-13 19:19:58 -04:00
Thomas Fleming
ae888b5705
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
2021-04-13 13:42:03 -04:00
Thomas Fleming
f0c926cf68
Move InstrPageFault to fetch stage
2021-04-13 13:39:22 -04:00
Teo Ene
0bffac2c74
Various code syntax changes to bring HDL to a synthesizable level
2021-04-13 11:27:12 -05:00
