David Harris
07f34c8263
.gitmodule added dirty riscv-arch-test
2021-12-29 23:50:17 +00:00
David Harris
3fdaa0ab2c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 23:49:16 +00:00
Ross Thompson
56d86f4dd5
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
ac5746c721
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
aa227ce97c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
60f0339690
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 14:48:16 -06:00
Ross Thompson
e36a037afa
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
James E. Stine
2339e3a483
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 13:01:27 -06:00
James E. Stine
2e5b805b0a
Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines
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Katherine/James
2021-12-29 12:59:17 -06:00
David Harris
ea42025901
Fixed .gitignore
2021-12-29 18:58:36 +00:00
David Harris
b6dd0b110c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 18:53:13 +00:00
David Harris
57d32e58c6
Switched riscv-arch-test to current hash
2021-12-29 18:52:52 +00:00
Ross Thompson
995cfb1cf3
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
bc6e776609
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
5ebaeb5d90
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
15f1627a31
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
a82af378e2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 21:28:12 -06:00
Ross Thompson
29b3285c8e
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
c3bfa53db0
Added partially working MMU tests
2021-12-29 03:14:16 +00:00
Ross Thompson
67a33a80f9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 20:22:36 -06:00
David Harris
40e0e6a401
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
d78b806332
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
d64fe4b1c1
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
a966764d88
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
7044277165
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
00ad3a18fb
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
fe5f016a16
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
c1789932a4
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
daac21b3bd
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
b6f4efd458
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
22bfc80e62
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
b4ab435bff
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
c2b0e61466
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
77e8ba619e
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
d6960da90e
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
3e7ec1e9a2
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
3ee29785a4
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
David Harris
52469db9ff
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
67bbb03897
Fixed exe2memfile.pl bug
2021-12-27 00:44:18 +00:00
David Harris
69243f41ad
Fixed imperas C tests
2021-12-26 04:45:06 +00:00
David Harris
a7cfda8e52
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
e97e512da9
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
35e31006a9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
37b091e5da
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
bc8370f4d8
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-23 12:40:42 -06:00
Ross Thompson
ae0cc085b4
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
David Harris
edef4524ae
added wallyVirtIO.patch from Ross
2021-12-22 07:04:47 -08:00
Ross Thompson
7b99df2f1c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-21 22:38:05 -06:00
Ross Thompson
42ad710213
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
