Ross Thompson
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07bb11518e
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Found a hidden bug in the cache to bus fsm interlock.
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2022-09-26 17:41:30 -05:00 |
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Ross Thompson
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996c4ca8f2
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renamed ahbmulticontroller to ebu.
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2022-09-26 14:37:18 -05:00 |
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Ross Thompson
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8ed173a5f5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-26 12:49:16 -05:00 |
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Ross Thompson
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0fcc314d06
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Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed.
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2022-09-26 12:48:26 -05:00 |
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Kip Macsai-Goren
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e603973dff
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added xlen and endianness test edits. xlen passes but endinanness still won't make
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2022-09-26 05:03:19 +00:00 |
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Kip Macsai-Goren
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61745f9804
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added simple post processing script to give branch miss proportion in coremark log
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2022-09-26 04:51:04 +00:00 |
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David Harris
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713df785d1
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changed always_ff to always in sram1p1rw to fix testbench complaint
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2022-09-25 19:56:40 -07:00 |
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Ross Thompson
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38edbde966
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Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
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2022-09-23 11:46:53 -05:00 |
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Ross Thompson
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2eaf3af6c7
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Removed the write first sram model.
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2022-09-22 16:12:08 -05:00 |
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Ross Thompson
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cec50ce208
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The valid and dirty bits match the SRAM implementation now.
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2022-09-22 16:09:09 -05:00 |
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Ross Thompson
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b48d6b5e1f
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Solved the sram write first / read first issue. Works correctly with read first now.
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2022-09-22 14:16:26 -05:00 |
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Ross Thompson
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89e6ddfa4e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 18:24:06 -05:00 |
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Ross Thompson
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99e01dd31f
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Cleaned up the IFU and LSU around dtim and irom address calculation.
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2022-09-21 18:23:56 -05:00 |
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David Harris
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d6297a2f2e
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For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc
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2022-09-21 13:30:35 -07:00 |
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David Harris
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e49e99548a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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46680b80a7
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Eliminated store after store stall when no cache; simplified divshiftcalc logic.
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2022-09-21 13:02:34 -07:00 |
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Ross Thompson
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f57b0b9950
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Updated IROMAdr logic.
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2022-09-21 12:42:43 -05:00 |
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Ross Thompson
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0add170b44
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:36:52 -05:00 |
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Ross Thompson
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3fb0a13fe2
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Moved other SRAMs to generic/mem.
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2022-09-21 12:36:03 -05:00 |
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David Harris
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030fb79a3c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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cb4c3ff1ce
|
Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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66c45949b5
|
Renamed brom1p1r to rom1p1r.
removed used file bram2p1r1w.sv.
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2022-09-21 12:31:20 -05:00 |
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Ross Thompson
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832658838d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 12:20:12 -05:00 |
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Ross Thompson
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ac864a6ca3
|
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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c0884ecc63
|
Modified sram1p1rw to support 3 different implementation styles.
SRAM, Read first, and Write first.
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2022-09-21 11:26:00 -05:00 |
|
David Harris
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129b9343fe
|
commented SpecialCase
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2022-09-21 05:02:08 -07:00 |
|
David Harris
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5e1932c649
|
Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc
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2022-09-21 04:55:43 -07:00 |
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David Harris
|
f7d272c315
|
Gated sticky bit in fdiv with SpecialCase
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2022-09-20 20:05:00 -07:00 |
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David Harris
|
1cbdd20778
|
Restored radix 2 to pass regression
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2022-09-20 19:30:16 -07:00 |
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David Harris
|
3b98881c4e
|
renamed u to udigit to avoid conflict with U
|
2022-09-20 19:29:23 -07:00 |
|
cturek
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6e300a667e
|
Fixed R4 Sqrt overshifting
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2022-09-21 00:05:36 +00:00 |
|
cturek
|
c3c764f0ba
|
Fixed fgen4
|
2022-09-20 20:00:01 +00:00 |
|
Ross Thompson
|
980b35d585
|
Merge branch 'tempMain' into main
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2022-09-20 13:57:38 -05:00 |
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Ross Thompson
|
1658edd21e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 11:56:53 -05:00 |
|
Ross Thompson
|
426ec6222b
|
Added chip enables to sram.
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2022-09-20 10:49:14 -05:00 |
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David Harris
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11fb39b373
|
Define LOGNORMSHIFTSZ
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2022-09-20 08:31:57 -07:00 |
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Ross Thompson
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822d989383
|
Added comment.
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2022-09-20 09:49:53 -05:00 |
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Ross Thompson
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4c3c517322
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-20 09:47:16 -05:00 |
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David Harris
|
00c15ec472
|
renamed q to u for unified digit selection
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2022-09-20 04:35:14 -07:00 |
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David Harris
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d01588d693
|
Removed D2 and D2b from radix2 stage
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2022-09-20 04:20:38 -07:00 |
|
David Harris
|
2ea7df1b6d
|
Simplified UM initialization
|
2022-09-20 04:18:12 -07:00 |
|
David Harris
|
0d5e80a4f0
|
fdivsqrtfgen4 comments
|
2022-09-20 04:13:21 -07:00 |
|
David Harris
|
653c458241
|
Moved fpu modules into subdirectories
|
2022-09-20 04:12:05 -07:00 |
|
David Harris
|
0ec1886b89
|
Partitioned fdivsqrt into one module per file and added file names to opening comments
|
2022-09-20 03:57:57 -07:00 |
|
David Harris
|
a05b6486b1
|
Simplified fdivsqrtpostproc QmM logic
|
2022-09-20 03:30:18 -07:00 |
|
David Harris
|
87cde2c427
|
make QmM size b+1 indpenedent of radix
|
2022-09-20 03:25:09 -07:00 |
|
David Harris
|
e455f41b97
|
clean up divshiftcalc
|
2022-09-20 03:19:50 -07:00 |
|
David Harris
|
211705eca2
|
clean up divshiftcalc
|
2022-09-20 03:17:29 -07:00 |
|
David Harris
|
d3b2a192eb
|
clean up divshiftcalc
|
2022-09-20 03:13:11 -07:00 |
|
David Harris
|
f5083803c2
|
clean up divshiftcalc
|
2022-09-20 03:08:25 -07:00 |
|