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Author SHA1 Message Date
Harshini Srinath
04a744c249 Update fcmp.sv 
Program clean up
 2023-06-10 19:35:58 -07:00
Harshini Srinath
ffada57ea2 Update fcmp.sv 
Program clean up
 2023-06-10 19:34:58 -07:00
Harshini Srinath
ec188987b8 Update fclassify.sv 
Program clean up
 2023-06-10 19:30:18 -07:00
Harshini Srinath
9422c3380d Update ebufsmarb.sv 
Program clean up
 2023-06-10 18:26:56 -07:00
Harshini Srinath
9dc72c9e54 Update controllerinput.sv 
Program clean up
 2023-06-10 18:26:06 -07:00
Harshini Srinath
cb236a9368 Update busfsm.sv 
Program clean up
 2023-06-10 18:25:18 -07:00
Harshini Srinath
7f2adf67ed Update buscachefsm.sv 
Program clean up
 2023-06-10 18:24:55 -07:00
Harshini Srinath
dbdb3c69d3 Update ahbinterface.sv 
Program clean up
 2023-06-10 18:18:16 -07:00
Harshini Srinath
e69c7212f3 Update ahbcacheinterface.sv 
Program clean up
 2023-06-10 18:15:53 -07:00
Harshini Srinath
dc0b95c4ac Program clean up 2023-06-10 18:13:40 -07:00
Harshini Srinath
aafa5d6ec3 Update ebu.sv 
Code clean up
 2023-06-09 08:53:27 -07:00
Harshini Srinath
570a628198 Update subcachelineread.sv 
Code clean up
 2023-06-09 08:50:51 -07:00
Harshini Srinath
c49232f0d2 Update cacheway.sv 
Code clean up
 2023-06-09 08:48:11 -07:00
Harshini Srinath
e7fb7403ef Update cacheLRU.sv 
Code clean up
 2023-06-09 08:43:38 -07:00
Harshini Srinath
19c1a0f99b Update cache.sv 
Formatting clean up
 2023-06-09 08:39:57 -07:00
David Harris
c56aba5e4f Merge pull request #317 from ross144/main 
Updated parameterization types.  Modelsim version 2022.1 did requires defaults to a 32 bit integer.  The base and ranges for the address decoder need to be larger.
 2023-06-09 07:34:42 -07:00
Ross Thompson
be32e0238a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-09 09:28:31 -05:00
Ross Thompson
a8a8422557 Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger. 2023-06-09 09:28:24 -05:00
David Harris
262b00131f Merge pull request #316 from ross144/main 
Fixed garbled output in embench
 2023-06-08 09:09:13 -07:00
Ross Thompson
39c8f11191 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
48e050de95 Merge pull request #315 from davidharrishmc/dev 
CoreMark runs without error after post processing script is removed
 2023-06-06 23:30:58 -04:00
David Harris
ef804a4145 Removed postprocessing script from Coremark because percentages are already computed 2023-06-06 20:12:13 -07:00
Ross Thompson
4ddbbd6948 Merge pull request #314 from davidharrishmc/dev 
Make and FP script improvements
 2023-06-06 12:38:26 -04:00
David Harris
25fef1c38c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-06-06 08:46:54 -07:00
David Harris
d5ca261bc7 Modified benchmarks/coremark/Makefile to clean addins/coremark as well 2023-06-06 08:46:44 -07:00
David Harris
75dc86ddc0 Merge pull request #313 from ross144/main 
Fix extraneous force in testbench which keep btb in reset.
 2023-06-06 08:41:34 -07:00
David Harris
c9ca5108b1 Merge pull request #312 from ross144/main 
Fixed typo in coremark makefile.
 2023-06-06 05:44:22 -07:00
Ross Thompson
918464c236 Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
4425946db8 Fixed typo in coremark makefile. 2023-06-05 11:49:16 -05:00
Ross Thompson
f146f68a8c Merge pull request #311 from stineje/main 
Update some bugs in FPU
 2023-06-05 12:19:08 -04:00
James Stine
ac3253203d Update fcvt tests for l.s/lu.s and s.l/s.lu that were missing 2023-06-05 11:03:59 -05:00
James Stine
3bd5bbce48 Update some spacing to make it look better 2023-06-05 11:03:06 -05:00
Ross Thompson
76fd76c155 Oups forgot to include updates to the lint script itself. 2023-05-31 11:00:38 -05:00
Ross Thompson
a963f0af3a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
169539f773 Cleanup parameterization for verilator 5.010. 2023-05-31 10:02:34 -05:00
David Harris
534b2fcbc2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-31 06:31:52 -07:00
David Harris
1831dfccc2 Fixed paths in creating division test vectors 2023-05-31 06:30:41 -07:00
David Harris
65dd99af0c Support all testfloat tests with parameterized design 2023-05-31 06:30:21 -07:00
Ross Thompson
f526519573 Merge pull request #307 from davidharrishmc/dev 
Assorted cleanup, including test vector generation
 2023-05-30 20:04:58 -04:00
David Harris
b5f70013b1 Clean up combined int/fp vector creation 2023-05-30 14:01:12 -07:00
David Harris
df57ccd885 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:53:28 -07:00
David Harris
8022a97a8b Merge pull request #306 from ross144/main 
fixed testfloat testbench for parameterization
 2023-05-30 13:53:14 -07:00
Ross Thompson
74013f23e1 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-30 15:51:19 -05:00
Ross Thompson
8648d0c25c Hacked it together, but I think testfloat is working. 2023-05-30 15:51:13 -05:00
David Harris
51d001889a Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-05-30 13:40:56 -07:00
David Harris
828a22303c Merge pull request #305 from ross144/main 
Fixed all do scripts for parameterization
 2023-05-30 13:40:44 -07:00
Ross Thompson
4939784b6f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-30 15:38:58 -05:00
Ross Thompson
09aa460ed8 Updated do files for parameterization. 2023-05-30 15:38:03 -05:00
David Harris
535a01cce8 Merge pull request #304 from ross144/main 
Fixes bug 203 and linux/ImperasDV mismatch at 571M instructions
 2023-05-30 13:37:00 -07:00
Ross Thompson
8e1476cb8c Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt. 
This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state.  Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state.  When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE.  There may still be a remaining bug here if the pipeline is stalled for another reason.  However I don't think it is possible by construction.  The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
 2023-05-30 15:20:24 -05:00