Commit Graph

261 Commits

Author SHA1 Message Date
Shriya Nadgauda
0282aebec7 updated pipeline tests 2021-05-03 22:07:36 -04:00
Noah Boorstin
9275f141f9 same but do that right this time 2021-04-28 14:27:28 -04:00
Noah Boorstin
fce3d6a8b1 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
d191bc6cc1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
14a69c1d06 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
922c8e450f ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
24bbb674d3 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Noah Boorstin
9cbc769083 minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
44d28dbd1c Icache integrated!
Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
bbracker
f921886451 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
7947858481 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
8d77012995 progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
9e40fb072c Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
46a1616079 thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
5687ab1c96 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
dc3ffc9244 Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Noah Boorstin
50df9d11e1 busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
2a5c243b0b adding pipeline testing 2021-04-23 14:19:17 -04:00
Ross Thompson
c9bdaceddb Fixed icache for 32 bit.
Merge branch 'cache' into main
2021-04-22 16:45:29 -05:00
Thomas Fleming
f9e071baf8 Temporarily disable rv64 mmu test
Will restore once cache revamp is pushed
2021-04-22 13:19:18 -04:00
Noah Boorstin
0afd5ae5f6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Domenico Ottolia
82320033d5 Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
fed42ffe19 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
d5f86fadac Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Noah Boorstin
c7a09d2359 yay buildroot passes a decent amount of tests now
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Noah Boorstin
10c7ac7f73 slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
d0a137ce0c neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
5902637632 buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
541fb22dc9 start to add buildroot testbench
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
bbracker
11cf251378 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
195cead01c working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
b1cd107a00 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
8c4cfa5f69 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Jarred Allen
7b4b1a31ef Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Thomas Fleming
d281ecd067 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
757b64e487 Merge branch 'main' into cache
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
2021-04-14 18:24:32 -04:00
bbracker
ccff1e6c99 rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
3e0ed5a2b1 busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
18a4d5fc8d busybear testbench updates
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
2021-04-14 00:00:27 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
bbracker
0c85b1c201 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
c8c87bd0d8 merge testbench 2021-04-08 14:28:01 -04:00
Noah Boorstin
5f1cd43033 try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
1bdfac6a77 Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
7f12c7af90 Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.

instr
addr   correct   got
2021-04-07 19:12:43 -05:00
Domenico Ottolia
9b82fbff5a Add privileged tests to testbench 2021-04-07 02:22:08 -04:00