Rose Thompson
57d1709582
The path to the zsbl was wrong all this time, but for reason was working with older versions of Ubuntu, but one 24.04 it causes vivado to not find the rom and ram.
2024-10-30 16:01:11 -05:00
Rose Thompson
d4fc3245b0
Removed ahbsdc submodule since it is no longer used. Updated old
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submodules pointing to ross144 to rosethompson repos.
2024-10-15 10:11:12 -05:00
Rose Thompson
510e3a268c
Added spi debugger to build script.
2024-09-05 12:04:14 -07:00
Rose Thompson
7e16ddd859
Improved fpga synth script.
2024-08-27 15:50:05 -07:00
Rose Thompson
e5d3462a90
Converted wall.tcl to entirely project mode.
2024-08-27 14:15:58 -07:00
Rose Thompson
f20a1564fa
Added SPI debugger.
2024-08-26 17:22:13 -07:00
Rose Thompson
167878aee4
Commet out debug code in fpga synth script.
2024-08-23 14:46:01 -07:00
Rose Thompson
4d56b3ca96
Maybe improvements to fpga synthesis.
2024-08-23 13:00:22 -07:00
Rose Thompson
fc80bf1251
More updates to fpga IP module names.
2024-08-22 14:31:39 -07:00
Rose Thompson
8d40a0a092
Changed names of fpga IP modules to match textbook. Updated boot.h to
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use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
2024-08-22 13:56:50 -07:00
Jacob Pease
8c96c06022
Commented out rvvi debug probes in wally.tcl.
2024-08-08 13:52:53 -05:00
Jacob Pease
954e21148f
Removed line referring to local file in wally.tcl.
2024-08-06 17:11:08 -05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
ebdf25a53b
Commented out references to old axi IP from wally.tcl.
2024-07-24 22:47:15 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
556c210e76
Added option to use rvvi ila
2024-07-22 12:19:37 -05:00
Jacob Pease
7ecd1c7d5f
The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.
2024-05-30 15:48:27 -05:00
Rose Thompson
26cd22c388
Replaced fpga's verilog top with system verilog.
2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c
Replaced fpga top level verilog with system verilog.
2023-12-15 13:07:08 -06:00
Jacob Pease
ff73f798ed
Replaced vivado-risc-v addins directory with new SDC repo.
2023-11-16 13:59:12 -06:00
Rose Thompson
f8b65f50b0
Fixed bugs in the updated fpga synthe script.
2023-11-13 18:10:22 -06:00
Rose Thompson
d5f0c15b90
Modified the fpga build script to generate it's own config file rather than use the one in config/fpga.
2023-11-13 17:48:28 -06:00
Jacob Pease
2bf6207919
Added help option to the flash-sd script.
2023-08-22 13:37:33 -05:00
Ross Thompson
fb1c1a1832
Added new signals to the vcu118 debug4 ila to help figure out why the new linux build's hptw fails.
2023-08-02 16:14:04 -05:00
Ross Thompson
c4ae856f92
Clean up vcu118 synth scripts.
2023-08-01 14:39:33 -05:00
Ross Thompson
06efd2cdde
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Ross Thompson
b1f7a5768f
Removed all old references to the old flash card controller.
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Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
2023-07-24 15:45:57 -05:00
Ross Thompson
a89a1e675c
Merge branch 'boot' into mergeBoot
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Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Jacob Pease
380d96b359
Working new boot process. Buildroot package for sdc.
2023-07-20 14:15:59 -05:00
Ross Thompson
a8f11dcad0
FPGA updates.
2023-06-20 11:11:34 -05:00
Ross Thompson
1a23f1360f
Updated fpga wally wrapper to work with the ILA.
2023-06-19 12:15:48 -05:00
Ross Thompson
0423d7df82
I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug.
2023-06-16 17:00:27 -05:00
Ross Thompson
443c568994
Vivado requires an intermediate wrapper file for parameterization.
2023-06-16 16:30:14 -05:00
Ross Thompson
c44d4321fb
FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
2023-06-16 15:40:13 -05:00
Ross Thompson
b0f0fb1da7
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
f4734c0d1b
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
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mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
2f8359e6cc
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
e490ab09cf
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
c4e5b8db49
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
5bcb0f6ace
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
0700202001
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Jacob Pease
45b264fa59
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-02-16 17:36:26 -06:00
David Harris
78eb90715c
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
Jacob Pease
07e279b5b5
Modified makefile. Added axi protocol converter IP.
2023-01-23 19:30:29 -06:00
Jacob Pease
293cc88bd9
Added extra core signal to mark_debug.txt. Modified wally.tcl
2023-01-23 17:00:24 -06:00
Jacob Pease
9b612fbf6c
Merge branch 'main' of github.com:openhwgroup/cvw into boot
2023-01-23 12:41:02 -06:00
Ross Thompson
0ed9811e31
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
5b740fbf60
Removed SDC from repo due to copy right issue.
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Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Jacob Pease
ee3a9537a8
Fixed errors in uncore and included newsdc stuff in wally.tcl
2023-01-17 16:46:00 -06:00
Jacob Pease
b618518907
Fixed typos. Apparently `defube causes a weird vivado error.
2023-01-13 16:59:18 -06:00
