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cvw/.gitignore

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Add the regression logs and new regression byproducts to the gitignore
2021-02-02 15:43:41 +00:00
**/work*
**/wally_*.log
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 22:55:05 +00:00
add .nfs* files to gitignore
2021-02-28 20:48:01 +00:00
.nfs*
Add vscode and pycache folders to .gitignore
2021-03-25 06:37:50 +00:00
__pycache__/
.vscode/
gitignore the addins folder because it contains external repos
2021-10-19 20:32:26 +00:00
#External repos
Fixed .gitignore
2021-12-29 18:58:36 +00:00
addins/riscv-arch-test/Makefile.include
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
addins/riscv-tests/target
Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M
2022-12-28 05:24:38 +00:00
addins/TestFloat-3e/build/Linux-x86_64-GCC/*
fixed typo in git ignore
2022-06-13 23:34:27 +00:00
benchmarks/embench/wally*.json
gitignore the addins folder because it contains external repos
2021-10-19 20:32:26 +00:00
More testbench setup work - Copy bare-bones testbench from E85 - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier - Create .gitignore for vsim files - Make PC reset a macro, change to 0x1000 to conform to the bootloader I don't know a good way to put the linux register trace file we're generating on git, since its both nontrivial to make and way to big to keep in a git repo for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 22:55:05 +00:00
#vsim work files to ignore
transcript
vsim.wlf
Removed pipelined level of hierarchy
2023-02-02 22:14:11 +00:00
wlft*
Busybear test now processes first 100 instrs correctly! - changed test parser to recognize lw in addition to lw also, added temporary questa files (wlft*) to .gitignore
2021-01-28 06:16:39 +00:00
wlft*
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
/imperas-riscv-tests/FunctionRadix_32.addr
/imperas-riscv-tests/FunctionRadix_64.addr
gitignore FunctionRadix.addr
2021-03-25 04:13:46 +00:00
/imperas-riscv-tests/FunctionRadix.addr
Added debug option to disable the function radix if not needed. Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
2021-03-10 21:17:02 +00:00
/imperas-riscv-tests/ProgramMap.txt
script for running make and logging output
2021-05-18 02:12:18 +00:00
/imperas-riscv-tests/logs
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-31 04:18:20 +00:00
*.o
*.d
Added files to repo
2021-12-05 04:25:33 +00:00
*.vstf
Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
2021-03-31 04:18:20 +00:00
testsBP/*/*/*.elf*
testsBP/*/OBJ/*
testsBP/*/*.a
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/*
arch bug fixes and testbench changes
2022-06-17 22:07:16 +00:00
tests/riscof/riscof_work/
added new work files to gitignore
2022-06-17 01:06:25 +00:00
tests/riscof/config32.ini
fixed wally rv32e tests, updated regression makefile to new testflow
2022-07-23 00:09:46 +00:00
tests/riscof/config32e.ini
added new work files to gitignore
2022-06-17 01:06:25 +00:00
tests/riscof/config64.ini
linux testgen refactor
2021-11-01 21:09:49 +00:00
tests/linux-testgen/linux-testvectors/*
!tests/linux-testgen/linux-testvectors/tvCopier.py
!tests/linux-testgen/linux-testvectors/tvLinker.sh
!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
tests/linux-testgen/buildroot
tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/slack-notifier/slack-webhook-url.txt
sim/logs
Created Makefile to manage IP generation.
2021-11-30 00:32:51 +00:00
fpga/generator/IP
Added make clean to fpga IP generator.
2021-11-30 00:42:28 +00:00
fpga/generator/vivado.*
Updated .gitignore file to hide fpga outputs.
2021-12-14 00:30:10 +00:00
fpga/generator/.Xil/*
fpga/generator/WallyFPGA*
fpga/generator/reports/
fpga/generator/*.log
fpga/generator/*.jou
Fixed .gitignore
2021-12-29 18:58:36 +00:00
*.objdump*
*.signature.output
examples/asm/sumtest/sumtest
lsu cleanup down to 346 lines
2022-01-15 01:19:44 +00:00
examples/asm/example/example
Updated configs to fix GPIO address to match FU540
2022-01-26 18:16:34 +00:00
examples/C/sum/sum
Replaced || and && with | and &
2022-01-31 01:07:35 +00:00
examples/C/fir/fir
Created softfloat_demo showcasing how to do math with SoftFloat
2022-02-27 18:17:21 +00:00
examples/fp/softfloat_demo/softfloat_demo
Enhanced printing intermediate results in fpcalc.c
2022-02-28 04:15:20 +00:00
examples/fp/fpcalc/fpcalc
ignore example binaries
2023-05-30 06:24:48 +00:00
examples/C/inline/inline
examples/C/sum_mixed/sum_mixed
examples/asm/trap/trap
Removed pipelined level of hierarchy
2023-02-02 22:14:11 +00:00
src/fma/fma16_testgen
add trimmed-down virt devicetree to repo for QEMU
2022-02-08 11:11:44 +00:00
linux/devicetree/debug/*
rename dump-dts debug script
2022-02-10 00:10:09 +00:00
!linux/devicetree/debug/dump-dts.sh
revived checkpointing and hacked it up to generate a trace starting at the checkpoint
2022-02-25 23:51:40 +00:00
linux/testvector-generation/genCheckpoint.gdb
linux/testvector-generation/silencePipe
linux/testvector-generation/silencePipe.control
linux/testvector-generation/fixBinMem
greatly improve trace-generating checkpoint process with QEMU hack
2022-02-28 23:00:00 +00:00
linux/testvector-generation/qemu-serial
gitignore dtb's because we only care about dts's as being source files
2022-02-08 11:14:59 +00:00
*.dtb
Cleaned up synthesis flow.
2022-02-09 21:18:49 +00:00
synthDC/WORK
synthDC/alib-52
synthDC/*.log
synthDC/*.svf
synthDC/runs/
organizing synth scripts
2022-06-24 06:43:44 +00:00
synthDC/newRuns
organized ppa files into ppa directory
2022-07-05 22:28:25 +00:00
synthDC/ppa/PPAruns
synthDC/ppa/plots
Fixed config file writing for synthesis (#29) * Fixed writing config files for synth sweeps * cleaned up comments
2023-01-26 04:58:15 +00:00
synthDC/wallyplots/
stop tracking runArchive and ppa plots
2022-06-03 22:03:26 +00:00
synthDC/runArchive
Cleaned up synthesis flow.
2022-02-09 21:18:49 +00:00
synthDC/hdl
Adjusted synthesis scripts to report on DESIGN even when a wrapper is used
2023-10-19 13:16:52 +00:00
synthDC/wrappers
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/power.saif
Added bootmem source ccode
2022-04-05 23:22:53 +00:00
tests/fp/vectors/*.tv
Ignore intermediate files in synthesis sweeps
2022-04-27 13:12:04 +00:00
synthDC/Summary.csv
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/wkdir
Added files to gitignore.
2022-12-19 00:53:37 +00:00
tests/custom/work
tests/custom/*/*/*.list
tests/custom/*/*/*.elf
tests/custom/*/*/*.map
tests/custom/*/*/*.memfile
tests/custom/crt0/*.a
More progress on debug.S, but it crashes in Spike
2023-02-04 17:59:22 +00:00
tests/custom/*/*.elf*
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/sd_model.log
Removed SDC from repo due to copy right issue. Modified fpga build flow to reference it outside the repo.
2023-01-20 20:35:46 +00:00
fpga/src/sdc/*
fpga/src/sdc.tar.gz
Updated ignore to exclude copied files.
2023-01-21 01:45:17 +00:00
fpga/src/CopiedFiles_do_not_add_to_repo/*
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/branch.log
Merge branch 'main' of https://github.com/openhwgroup/cvw This merges the branch predictor improvements into the main repo.
2023-01-29 21:24:20 +00:00
/fpga/generator/sim/imp-funcsim.v
/fpga/generator/sim/imp-timesim.sdf
/fpga/generator/sim/imp-timesim.v
/fpga/generator/sim/syn-funcsim.v
ignore external
2023-01-18 13:22:32 +00:00
external
Renamed regression to sim
2023-02-02 22:48:23 +00:00
sim/results
Ignore new tests from lab
2023-02-15 14:43:00 +00:00
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
Improved coverage reporting
2023-03-19 17:24:35 +00:00
sim/branch_BP_GSHARE10.log
sim/branch_BP_GSHARE16.log
sim/cov/
sim/covhtmlreport/
sim/imperas.log
sim/results-error/
sim/test1.rep
Ignore more log files left from ImperasDV
2023-03-19 17:26:53 +00:00
sim/vsim.log
Makefile improvements
2023-03-22 18:17:17 +00:00
tests/coverage/*.elf
Git issues, repushing
2023-03-29 11:10:47 +00:00
*.elf.memfile
sim/*Cache.log
Ignore IF_vectors
2023-04-28 13:20:12 +00:00
sim/branch
tests/fp/combined_IF_vectors/IF_vectors/*.tv
Fpga does not correctly boot linux. I think the solution here is to revert out all substantive changes except for parameterization and then add them back in one at a time. This is necessary because the parameterization is not completed in one contiguous group of commits.
2023-06-22 17:55:49 +00:00
/sim/branch-march14.tar.gz
/sim/gshareforward-no-class
/sim/lint-wally_32
/sim/lint-wally_32e
/sim/local16.txt
/sim/localhistory_m6k10_results_april24.txt
/sim/log.log
/sim/obj_dir/Vtestbench.cpp
/sim/obj_dir/Vtestbench.h
/sim/obj_dir/Vtestbench.mk
/sim/obj_dir/Vtestbench__ConstPool_0.cpp
/sim/obj_dir/Vtestbench__Syms.cpp
/sim/obj_dir/Vtestbench__Syms.h
/sim/obj_dir/Vtestbench___024root.h
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__10.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__11.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__1__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__2__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__3__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__4__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__5__Slow.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__6.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__7.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__8.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hed41eec4__9.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0.cpp
/sim/obj_dir/Vtestbench___024root__DepSet_hfc24d085__0__Slow.cpp
/sim/obj_dir/Vtestbench___024root__Slow.cpp
/sim/obj_dir/Vtestbench___024unit.h
/sim/obj_dir/Vtestbench___024unit__DepSet_hf87c9ffd__0__Slow.cpp
/sim/obj_dir/Vtestbench___024unit__Slow.cpp
/sim/obj_dir/Vtestbench__verFiles.dat
/sim/obj_dir/Vtestbench_classes.mk
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9.h
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h34d4af8f__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__DepSet_h845a114e__1.cpp
/sim/obj_dir/Vtestbench_tlbcam__Pz1_T20_K34_S9__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20.h
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_h3df7cb71__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__DepSet_hab70f5b0__0__Slow.cpp
/sim/obj_dir/Vtestbench_tlbram__Pz1_T20__Slow.cpp
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