forked from Github_Repos/cvw
220 lines
11 KiB
Systemverilog
220 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// hptw.sv
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//
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// Written: tfleming@hmc.edu 2 March 2021
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// Modified: david_harris@hmc.edu 18 July 2021 cleanup and simplification
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// kmacsaigoren@hmc.edu 1 June 2021
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// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
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// adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
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// adding the internal SvMode signal
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//
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// Purpose: Page Table Walker
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// Part of the Memory Management Unit (MMU)
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module hptw
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(
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input logic clk, reset,
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input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
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input logic [`XLEN-1:0] PCF, IEUAdrM, // addresses to translate
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input logic ITLBMissF, DTLBMissM, // TLB Miss
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input logic [1:0] MemRWM, // 10 = read, 01 = write
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input logic [`XLEN-1:0] HPTWReadPTE, // page table entry from LSU
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input logic DCacheStall, // stall from LSU
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input logic MemAfterIWalkDone,
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input logic AnyCPUReqM,
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output logic [`XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic HPTWStall,
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output logic [`PA_BITS-1:0] TranslationPAdr,
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output logic HPTWRead, // HPTW requesting to read memory
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output logic WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
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);
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typedef enum {L0_ADR, L0_RD,
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L1_ADR, L1_RD,
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L2_ADR, L2_RD,
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L3_ADR, L3_RD,
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LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
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generate
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if (`MEM_VIRTMEM) begin
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logic DTLBWalk; // register TLBs translation miss requests
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic MemWrite;
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logic Executable, Writable, Readable, Valid;
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logic Misaligned, MegapageMisaligned;
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logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
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logic StartWalk;
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logic TLBMiss;
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logic PRegEn;
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logic [1:0] NextPageType;
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logic [`SVMODE_BITS-1:0] SvMode;
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logic [`XLEN-1:0] TranslationVAdr;
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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// Extract bits from CSRs and inputs
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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assign MemWrite = MemRWM[0];
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assign TLBMiss = (DTLBMissM | ITLBMissF);
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// Determine which address to translate
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assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
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assign CurrentPPN = PTE[`PPN_BITS+9:10];
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// State flops
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flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
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assign PRegEn = HPTWRead & ~DCacheStall;
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flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
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// Assign PTE descriptors common across all XLEN values
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// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
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assign {Executable, Writable, Readable, Valid} = PTE[3:0];
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign ValidLeafPTE = ValidPTE & LeafPTE;
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assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
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// Enable and select signals based on states
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assign StartWalk = (WalkerState == IDLE) & TLBMiss;
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assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
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assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
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assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
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assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
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// Raise faults. DTLBMiss
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assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
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assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBWalk & ~MemWrite;
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assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBWalk & MemWrite;
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// FSM to track PageType based on the levels of the page table traversed
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flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
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always_comb
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case (WalkerState)
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L3_RD: NextPageType = 2'b11; // terapage
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L2_RD: NextPageType = 2'b10; // gigapage
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L1_RD: NextPageType = 2'b01; // megapage
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L0_RD: NextPageType = 2'b00; // kilopage
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default: NextPageType = PageType;
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endcase
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// TranslationPAdr muxing
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if (`XLEN==32) begin // RV32
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logic [9:0] VPN;
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logic [`PPN_BITS-1:0] PPN;
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assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
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assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN;
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assign TranslationPAdr = {PPN, VPN, 2'b00};
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end else begin // RV64
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logic [8:0] VPN;
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logic [`PPN_BITS-1:0] PPN;
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always_comb
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case (WalkerState) // select VPN field based on HPTW state
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L3_ADR, L3_RD: VPN = TranslationVAdr[47:39];
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L2_ADR, L2_RD: VPN = TranslationVAdr[38:30];
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L1_ADR, L1_RD: VPN = TranslationVAdr[29:21];
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default: VPN = TranslationVAdr[20:12];
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endcase
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assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) |
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(SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
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assign TranslationPAdr = {PPN, VPN, 3'b000};
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end
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// Initial state and misalignment for RV32/64
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if (`XLEN == 32) begin
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assign InitialWalkerState = L1_ADR;
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assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
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// *** Possible bug - should be L1_ADR?
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assign Misaligned = ((WalkerState == L0_ADR) & MegapageMisaligned);
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end else begin
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logic GigapageMisaligned, TerapageMisaligned;
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assign InitialWalkerState = (SvMode == `SV48) ? L3_ADR : L2_ADR;
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assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
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assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
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assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
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assign Misaligned = ((WalkerState == L2_ADR) & TerapageMisaligned) | ((WalkerState == L1_ADR) & GigapageMisaligned) | ((WalkerState == L0_ADR) & MegapageMisaligned);
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end
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// Page Table Walker FSM
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// If the setup time on the D$ RAM is short, it should be possible to merge the LEVELx_READ and LEVELx states
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// to decrease the latency of the HPTW. However, if the D$ is a cycle limiter, it's better to leave the
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// HPTW as shown below to keep the D$ setup time out of the critical path.
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// *** Is this really true. Talk with Ross. Seems like it's the next state logic on critical path instead.
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb
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case (WalkerState)
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IDLE: if (TLBMiss) NextWalkerState = InitialWalkerState;
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else NextWalkerState = IDLE;
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
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else NextWalkerState = L2_ADR;
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// LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
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// else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
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// else NextWalkerState = FAULT;
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L2_ADR: if (InitialWalkerState == L2_ADR) NextWalkerState = L2_RD; // first access in SV39
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else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
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else NextWalkerState = FAULT;
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L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
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else NextWalkerState = L1_ADR;
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// LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
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// else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
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// else NextWalkerState = FAULT;
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L1_ADR: if (InitialWalkerState == L1_ADR) NextWalkerState = L1_RD; // first access in SV32
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else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
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else NextWalkerState = FAULT;
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L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
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else NextWalkerState = L0_ADR;
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// LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
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// else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
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// else NextWalkerState = FAULT;
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L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
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else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else NextWalkerState = FAULT;
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L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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// LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
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// else NextWalkerState = FAULT;
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LEAF: if (DTLBWalk) NextWalkerState = IDLE; // updates TLB
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else NextWalkerState = IDLE;
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LEAF_DELAY: NextWalkerState = IDLE; // give time to allow address translation
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FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
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else NextWalkerState = IDLE;
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default: begin
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// synthesis translate_off
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$error("Default state in HPTW should be unreachable");
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// synthesis translate_on
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NextWalkerState = IDLE; // should never be reached
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end
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endcase
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end else begin // No Virtual memory supported; tie HPTW outputs to 0
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assign HPTWRead = 0;
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assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
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assign TranslationPAdr = 0;
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end
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endgenerate
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endmodule
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