Ross Thompson
f4d778c2f6
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
a445bedcd2
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
...
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
ee81cfff0c
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
James E. Stine
02a1fda650
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
a70d51f4c9
Modified the hptw's simulation error message so that synthesis does not attempt to include this statement.
2021-08-16 10:02:29 -05:00
Ross Thompson
ef55b30e99
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
kipmacsaigoren
f3579032bd
Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's
2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332
Removed LEVELx states from HPTW
2021-07-23 08:11:15 -04:00
Ross Thompson
4d53b9002f
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
4f8f52f283
Added FLEN, NE, NF to config and started using these in FMA1
2021-07-18 17:28:25 -04:00
David Harris
8317be5aed
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
