cvw/pipelined/src/fpu
2022-12-22 00:43:27 +00:00
..
fdivsqrt Renamed signals to E and M stages, forwarded preprocessed n to fsm 2022-12-22 00:43:27 +00:00
fma Removed unused FPU signals 2022-12-21 11:31:22 -08:00
postproc Removed unused FPU signals 2022-12-21 11:31:22 -08:00
fclassify.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fcmp.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fctrl.sv Properly decode fcvtint to prevent unnecessary stalls 2022-12-19 09:09:48 -08:00
fcvt.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fhazard.sv Renamed FStallD to FPUStallD. 2022-12-19 09:28:45 -06:00
fpu.sv Removed unused FPU signals 2022-12-21 11:31:22 -08:00
fregfile.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fsgninj.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
normshift.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpack.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpackinput.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00