Ross Thompson bd7343b791 Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.		2022-02-16 15:22:19 -06:00
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sdc	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
clint.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
gpio.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
plic.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
ram.sv	Updated fpga's bootloader to reflect the changes to the gpio address change.	2022-02-01 10:43:24 -06:00
subwordwrite.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
uart.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
uartPC16550D.sv	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
uncore.sv	Modified lsu and uncore so only 1 sww is present. The sww is in the LSU if there is a cache or dtim. uncore.sv contains the sww if there is no local memory in the LSU. This is necessary as the subword write needs the read data to be valid and that read data is not aviable in the correct cycle in the LSU if there is no dtim or cache. Muxing could be done to provide the correct read data, but it adds muxes to the critical path.	2022-02-16 15:22:19 -06:00