bbracker cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset		2021-07-19 15:13:03 -04:00
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clint.sv	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
dtim.sv	Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries	2021-07-04 11:39:59 -04:00
gpio.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
plic.sv	Simplified PLIC with generate	2021-07-04 19:17:15 -04:00
subwordwrite.sv	Data memory bus integration	2021-02-07 23:21:55 -05:00
uart.sv	rv64 interrupt servicing	2021-04-14 10:19:42 -04:00
uartPC16550D.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
uncore.sv	Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.	2021-07-04 01:19:38 -04:00