..
slack-notifier
added instructions to slack notifier
2022-05-18 16:50:31 -07:00
wave-dos
Added generate around uncore.
2022-08-25 10:35:24 -05:00
wkdir
added wkdir in regression so regression runs out of box (assuming the old version of arch tests)
2022-05-17 20:32:38 +00:00
buildrootBugFinder.py
update to match new filesystem organization
2022-03-26 21:28:32 +00:00
fpga-wave.do
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
2022-09-21 12:20:00 -05:00
lint-wally
Made simple RV64 configuration be RV64i. Eliminated rv64ic and rv64fp. Fixed some bugs related to new width
2022-10-10 09:10:55 -07:00
linux-wave.do
Merged together bram1p1rw with sram1p1rw as sram1p1rw.
2022-09-21 12:20:00 -05:00
make-tests.sh
simplified make-tests.sh to run the current makefile in regression
2022-05-17 17:29:34 -07:00
Makefile
More riscof makefile tuning
2022-07-25 21:15:56 +00:00
makefile-memfile
plic-s debug
2022-08-03 12:33:09 +00:00
regression-wally
Removed imperas tests from rv32i/rv64i because the configs lack privileged support expected in the tests. Also cleaned up comment in LSU
2022-10-10 10:22:12 -07:00
sim-buildroot
switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
2022-03-01 03:11:43 +00:00
sim-buildroot-batch
sim-buildroot-batch now runs wally-pipelined-batch
2022-07-06 18:06:43 -07:00
sim-testfloat
Running 16-bit square root cases first in testfloat
2022-09-07 11:11:35 -07:00
sim-testfloat-batch
fixed error in divsqrt
2022-07-14 18:16:00 +00:00
sim-wally
Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.
2022-08-27 20:31:09 -07:00
sim-wally-batch
Renamed endianswap to match module name
2022-10-04 17:33:49 +00:00
testfloat.do
Moved fpu modules into subdirectories
2022-09-20 04:12:05 -07:00
wally-harvard.do
Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
2022-10-11 10:47:13 -05:00
wally-pipelined.do
Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.
2022-10-11 10:47:13 -05:00
wave-all.do
Added generate around uncore.
2022-08-25 10:35:24 -05:00
wave-fpu.do
Removed unused otfc for Q
2022-09-19 00:43:27 -07:00
wave.do
Updated wavefile.
2022-10-05 14:55:40 -05:00
403daecc8e