Ross Thompson b146c71b14 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2021-12-30 18:10:36 -06:00
..
common	Simplified ALU and source multiplexers pass tests	2021-12-13 07:57:38 -08:00
fp	CoreMark testing	2021-11-18 16:14:25 -08:00
sdc	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
imperas-boottim.txt	added sfence to legal instructions, zeroed out rom file to populate for tests	2021-07-23 15:55:08 -04:00
testbench-coremark_bare.sv	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
testbench-coremark.sv	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
testbench-f64.sv	Clean up some signals - beautification onging	2021-10-14 17:12:00 -05:00
testbench-fpga.sv	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
testbench-linux.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-12-30 18:10:36 -06:00
testbench-privileged.sv	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
testbench.sv	Patched up the linux-wave.do file.	2021-12-30 17:53:43 -06:00
tests.vh	Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion	2021-12-30 17:22:18 +00:00