cvw/wally-pipelined/src/fpu
2021-10-08 17:47:54 -05:00
..
adderparts.sv rename adder in fpu for synthesis 2021-10-08 17:47:54 -05:00
cla12.sv fpu cleanup 2021-07-24 14:59:57 -04:00
cla52.sv fpu cleanup 2021-07-24 14:59:57 -04:00
cla64.sv fpu cleanup 2021-07-24 14:59:57 -04:00
convert_inputs_div.sv fpu cleanup 2021-07-24 14:59:57 -04:00
convert_inputs.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
cvtfp.sv move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
divconv.sv fpu cleanup 2021-07-24 14:59:57 -04:00
exception_div.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
exception.sv all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
faddcvt.sv LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
fclassify.sv fpu cleanup 2021-07-24 14:59:57 -04:00
fcmp.sv fpu unpacking unit created 2021-07-14 17:56:49 -04:00
fctrl.sv all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
fcvt.sv all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
fhazard.sv all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
fma.sv FMA cleanup 2021-08-28 10:53:35 -04:00
fpdiv.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
fpu.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
fpudivsqrtrecur.sv Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
fpudivsqrtrecurcore.sv Modified rxfull determination in UART, started division 2021-09-12 20:00:24 -04:00
fregfile.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
fsgn.sv fpu cleanup 2021-07-24 14:59:57 -04:00
fsm.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
lzd_denorm.sv fpu cleanup 2021-07-24 14:59:57 -04:00
rounder_denorm.sv all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
rounder_div.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_a0.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_a1.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_a2.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_a3.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_div.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
sbtm_sqrt.sv Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
shifter_denorm.sv fpu cleanup 2021-07-24 14:59:57 -04:00
unpacking.sv all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00