forked from Github_Repos/cvw
164 lines
5.3 KiB
Systemverilog
Executable File
164 lines
5.3 KiB
Systemverilog
Executable File
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// MJS - This module implements a 57-bit 2-to-1 multiplexor, which is
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// used in the barrel shifter for significand alignment.
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module mux21x57 (Z, A, B, Sel);
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input [56:0] A;
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input [56:0] B;
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input Sel;
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output [56:0] Z;
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assign Z = Sel ? B : A;
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endmodule // mux21x57
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// MJS - This module implements a 64-bit 2-to-1 multiplexor, which is
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// used in the barrel shifter for significand normalization.
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module mux21x64 (Z, A, B, Sel);
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input [63:0] A;
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input [63:0] B;
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input Sel;
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output [63:0] Z;
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assign Z = Sel ? B : A;
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endmodule // mux21x64
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// The implementation of the barrel shifter was modified to use
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// fewer gates. It is now implemented using six 64-bit 2-to-1 muxes. The
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// barrel shifter takes a 64-bit input A and shifts it left by up to
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// 63-bits, as specified by Shift, to produce a 63-bit output Z.
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// Bits to the right are filled with zeros.
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// The 64 bit shift is implemented using 6 stages of shifts of 32
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// 16, 8, 4, 2, and 1 bit shifts.
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module barrel_shifter_l64 (Z, A, Shift);
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input [63:0] A;
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input [5:0] Shift;
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wire [63:0] stage1;
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wire [63:0] stage2;
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wire [63:0] stage3;
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wire [63:0] stage4;
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wire [63:0] stage5;
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wire [31:0] thirtytwozeros = 32'h0;
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wire [15:0] sixteenzeros = 16'h0;
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wire [ 7:0] eightzeros = 8'h0;
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wire [ 3:0] fourzeros = 4'h0;
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wire [ 1:0] twozeros = 2'b00;
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wire onezero = 1'b0;
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output [63:0] Z;
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mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]);
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mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]);
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mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]);
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mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]);
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mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]);
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mux21x64 mx06(Z , stage5, {stage5[62:0], onezero}, Shift[0]);
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endmodule // barrel_shifter_l63
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// The implementation of the barrel shifter was modified to use
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// fewer gates. It is now implemented using six 57-bit 2-to-1 muxes. The
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// barrel shifter takes a 57-bit input A and right shifts it by up to
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// 63-bits, as specified by Shift, to produce a 57-bit output Z.
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// It also computes a Sticky bit, which is set to
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// one if any of the bits that were shifted out was one.
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// Bits shifted into the left are filled with zeros.
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// The 63 bit shift is implemented using 6 stages of shifts of 32
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// 16, 8, 4, 2, and 1 bits.
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module barrel_shifter_r57 (Z, Sticky, A, Shift);
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input [56:0] A;
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input [5:0] Shift;
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output Sticky;
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output [56:0] Z;
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wire [56:0] stage1;
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wire [56:0] stage2;
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wire [56:0] stage3;
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wire [56:0] stage4;
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wire [56:0] stage5;
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wire [62:0] sixtythreezeros = 63'h0;
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wire [31:0] thirtytwozeros = 32'h0;
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wire [15:0] sixteenzeros = 16'h0;
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wire [ 7:0] eightzeros = 8'h0;
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wire [ 3:0] fourzeros = 4'h0;
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wire [ 1:0] twozeros = 2'b00;
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wire onezero = 1'b0;
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wire [62:0] S;
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// Shift operations
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mux21x57 mx01(stage1, A, {thirtytwozeros, A[56:32]}, Shift[5]);
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mux21x57 mx02(stage2, stage1, {sixteenzeros, stage1[56:16]}, Shift[4]);
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mux21x57 mx03(stage3, stage2, {eightzeros, stage2[56:8]}, Shift[3]);
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mux21x57 mx04(stage4, stage3, {fourzeros, stage3[56:4]}, Shift[2]);
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mux21x57 mx05(stage5, stage4, {twozeros, stage4[56:2]}, Shift[1]);
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mux21x57 mx06(Z , stage5, {onezero, stage5[56:1]}, Shift[0]);
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// Sticky bit calculation. The Sticky bit is set to one if any of the
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// bits that were shifter out were one
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assign S[31:0] = {32{Shift[5]}} & A[31:0];
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assign S[47:32] = {16{Shift[4]}} & stage1[15:0];
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assign S[55:48] = { 8{Shift[3]}} & stage2[7:0];
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assign S[59:56] = { 4{Shift[2]}} & stage3[3:0];
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assign S[61:60] = { 2{Shift[1]}} & stage4[1:0];
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assign S[62] = Shift[0] & stage5[0];
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assign Sticky = (S != sixtythreezeros);
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endmodule // barrel_shifter_r57
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/*
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module barrel_shifter_r64 (Z, Sticky, A, Shift);
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input [63:0] A;
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input [5:0] Shift;
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output Sticky;
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output [63:0] Z;
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wire [63:0] stage1;
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wire [63:0] stage2;
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wire [63:0] stage3;
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wire [63:0] stage4;
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wire [63:0] stage5;
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wire [62:0] sixtythreezeros = 63'h0;
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wire [31:0] thirtytwozeros = 32'h0;
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wire [15:0] sixteenzeros = 16'h0;
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wire [ 7:0] eightzeros = 8'h0;
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wire [ 3:0] fourzeros = 4'h0;
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wire [ 1:0] twozeros = 2'b00;
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wire onezero = 1'b0;
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wire [62:0] S;
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// Shift operations
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mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]);
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mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]);
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mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]);
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mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]);
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mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]);
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mux21x64 mx06(Z , stage5, {onezero, stage5[63:1]}, Shift[0]);
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// Sticky bit calculation. The Sticky bit is set to one if any of the
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// bits that were shifter out were one
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assign S[31:0] = {32{Shift[5]}} & A[31:0];
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assign S[47:32] = {16{Shift[4]}} & stage1[15:0];
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assign S[55:48] = { 8{Shift[3]}} & stage2[7:0];
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assign S[59:56] = { 4{Shift[2]}} & stage3[3:0];
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assign S[61:60] = { 2{Shift[1]}} & stage4[1:0];
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assign S[62] = Shift[0] & stage5[0];
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assign Sticky = (S != sixtythreezeros);
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endmodule // barrel_shifter_r64
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*/ |