forked from Github_Repos/cvw
103 lines
4.5 KiB
Systemverilog
Executable File
103 lines
4.5 KiB
Systemverilog
Executable File
module divconv (
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input logic [52:0] d, n,
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input logic [2:0] sel_muxa, sel_muxb,
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input logic sel_muxr,
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input logic load_rega, load_regb, load_regc, load_regd,
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input logic load_regr, load_regs,
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input logic P,
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input logic op_type,
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input logic exp_odd,
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input logic reset,
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input logic clk,
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output logic [63:0] q1, qp1, qm1,
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output logic [63:0] q0, qp0, qm0,
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output logic [63:0] rega_out, regb_out, regc_out, regd_out,
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output logic [127:0] regr_out
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);
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logic [63:0] muxa_out, muxb_out;
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logic [10:0] ia_div, ia_sqrt;
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logic [63:0] ia_out;
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logic [127:0] mul_out;
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logic [63:0] q_out1, qm_out1, qp_out1;
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logic [63:0] q_out0, qm_out0, qp_out0;
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logic [63:0] mcand, mplier, mcand_q;
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logic [63:0] twocmp_out;
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logic [64:0] three;
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logic [127:0] Carry, Carry2;
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logic [127:0] Sum, Sum2;
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logic [127:0] constant, constant2;
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logic [63:0] q_const, qp_const, qm_const;
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logic [63:0] d2, n2;
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logic [11:0] d3;
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logic muxr_out;
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logic cout1, cout2, cout3, cout4, cout5, cout6, cout7;
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// Check if exponent is odd for sqrt
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// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA
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assign d2 = (exp_odd&op_type) ? {1'b0,d,10'h0} : {d,11'h0};
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assign n2 = op_type ? d2 : {n,11'h0};
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// IA div/sqrt
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sbtm_div ia1 (d[52:41], ia_div);
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sbtm_sqrt ia2 (d2[63:52], ia_sqrt);
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assign ia_out = op_type ? {ia_sqrt, {53{1'b0}}} : {ia_div, {53{1'b0}}};
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// Choose IA or iteration
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mux6 #(64) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out);
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mux5 #(64) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out);
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// Deal with remainder if [0.5, 1) instead of [1, 2)
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mux2 #(128) mx3a ({~n, {75{1'b1}}}, {{1'b1}, ~n, {74{1'b1}}}, q1[63], constant2);
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// Select Mcand, Remainder/Q''
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mux2 #(128) mx3 (128'h0, constant2, sel_muxr, constant);
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// Select mcand - remainder should always choose q1 [1,2) because
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// adjustment of N in the from XX.FFFFFFF
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mux2 #(64) mx4 (q0, q1, q1[63], mcand_q);
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mux2 #(64) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier);
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mux2 #(64) mx6 (muxa_out, mcand_q, sel_muxr, mcand);
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// Q*D - N (reversed but changed in rounder.v to account for sign reversal)
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// Add ulp for subtraction in remainder
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mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out);
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// Constant for Q''
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mux2 #(64) mx8 ({64'h0000_0000_0000_0200}, {64'h0000_0040_0000_0000}, P, q_const);
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mux2 #(64) mx9 ({64'h0000_0000_0000_0A00}, {64'h0000_0140_0000_0000}, P, qp_const);
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mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const);
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// CPA (from CSA)/Remainder addition/subtraction
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assign {cout1, mul_out} = (mcand*mplier) + constant + muxr_out;
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// Assuming [1,2) - q1
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assign {cout2, q_out1} = regb_out + q_const;
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assign {cout3, qp_out1} = regb_out + qp_const;
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assign {cout4, qm_out1} = regb_out + qm_const + 1'b1;
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// Assuming [0.5,1) - q0
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assign {cout5, q_out0} = {regb_out[62:0], 1'b0} + q_const;
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assign {cout6, qp_out0} = {regb_out[62:0], 1'b0} + qp_const;
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assign {cout7, qm_out0} = {regb_out[62:0], 1'b0} + qm_const + 1'b1;
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// One's complement instead of two's complement (for hw efficiency)
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assign three = {~mul_out[126], mul_out[126], ~mul_out[125:63]};
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mux2 #(64) mxTC (~mul_out[126:63], three[64:1], op_type, twocmp_out);
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// regs
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flopenr #(64) regc (clk, reset, load_regc, twocmp_out, regc_out);
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flopenr #(64) regb (clk, reset, load_regb, mul_out[126:63], regb_out);
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flopenr #(64) rega (clk, reset, load_rega, mul_out[126:63], rega_out);
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flopenr #(64) regd (clk, reset, load_regd, mul_out[126:63], regd_out);
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flopenr #(128) regr (clk, reset, load_regr, mul_out, regr_out);
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// Assuming [1,2)
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flopenr #(64) rege (clk, reset, load_regs, {q_out1[63:39], (q_out1[38:10] & {29{~P}}), 10'h0}, q1);
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flopenr #(64) regf (clk, reset, load_regs, {qm_out1[63:39], (qm_out1[38:10] & {29{~P}}), 10'h0}, qm1);
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flopenr #(64) regg (clk, reset, load_regs, {qp_out1[63:39], (qp_out1[38:10] & {29{~P}}), 10'h0}, qp1);
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// Assuming [0,1)
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flopenr #(64) regh (clk, reset, load_regs, {q_out0[63:39], (q_out0[38:10] & {29{~P}}), 10'h0}, q0);
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flopenr #(64) regj (clk, reset, load_regs, {qm_out0[63:39], (qm_out0[38:10] & {29{~P}}), 10'h0}, qm0);
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flopenr #(64) regk (clk, reset, load_regs, {qp_out0[63:39], (qp_out0[38:10] & {29{~P}}), 10'h0}, qp0);
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endmodule // divconv
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