David Harris 8a43d6099b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2022-05-03 18:32:04 +00:00
..
cache	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-05-03 08:53:35 -07:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fma	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
fpu	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
generic	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
hazard	Extended sim time to fully boot Linux. Added comments to hazard unit	2022-04-24 13:51:00 +00:00
ieu	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
ifu	Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)	2022-04-22 22:46:11 +00:00
lsu	LSU name cleanup	2022-04-18 03:18:38 +00:00
mmu	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
uncore	Changed loop variable in CLINT because of error only seen on VLSI	2022-05-03 10:10:28 +00:00
wally	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00