Ross Thompson 5642918ead Merge branch 'main' into fpga		2021-11-29 10:06:53 -06:00
..
flop	Converted flops to synchronous reset now that reset signal is synchronized	2021-10-25 11:49:20 -07:00
adder.sv	More divider cleanup	2021-10-03 00:20:35 -04:00
arrs.sv	Changed several things.	2021-11-12 11:13:50 -06:00
clockgater.sv	Partially working sd card reader.	2021-10-11 10:23:45 -05:00
counter.sv	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
lzd.sv	Reversed [0:...] with [...:0] in bus widths across the project	2021-06-21 01:17:08 -04:00
mux.sv	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
neg.sv	SRT Division unsigned passing Imperas tests	2021-09-30 12:17:24 -04:00
onehotdecoder.sv	simplified or_rows generation and renamed oneHotDecoder to onehotdecoder	2021-08-25 06:46:41 -04:00
or_rows.sv	Fixed bug with or_rows.	2021-09-11 15:51:11 -05:00
shift.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00