cvw/pipelined/regression
2022-04-05 23:22:53 +00:00
..
slack-notifier
wave-dos
wkdir
buildrootBugFinder.py
fpga-wave.do Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
lint-wally
linux-wave.do add AtemptedInstructionCount signal 2022-03-26 21:28:57 +00:00
make-tests.sh
Makefile
makefile-memfile
regression-wally added RV64IA config to have a config without compressed instructions 2022-04-02 18:24:08 +00:00
sim-buildroot
sim-buildroot-batch
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally
sim-wally-batch
wally-coremark.do
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do
wally-pipelined-batch.do Added bootmem source ccode 2022-04-05 23:22:53 +00:00
wally-pipelined-fpga.do fpga simulation works again. 2022-04-03 17:31:07 -05:00
wally-pipelined.do Added bootmem source ccode 2022-04-05 23:22:53 +00:00
wave-all.do
wave-coremark.do
wave.do expand WALLY-PERIPH test to use SEIP on PLIC context 1 2022-03-31 18:02:06 -07:00