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old
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bringing Coremark back to life
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2021-11-10 12:43:31 -08:00 |
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slack-notifier
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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wave-dos
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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buildrootBugFinder.py
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automatic bug finder script
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2021-11-19 20:25:00 -08:00 |
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fpga-wave.do
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Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
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2021-11-17 12:47:19 -06:00 |
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lint-wally
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Added synchronizer to reset
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2021-10-25 10:05:41 -07:00 |
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linux-wave.do
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fix parseState.py to correctly take in PMPCFG
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2021-11-24 16:52:51 -08:00 |
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make-tests.sh
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add buildroot tv linking to make-tests.sh
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2021-12-07 11:15:59 -08:00 |
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Makefile
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root level makefile added
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2021-11-17 12:17:56 -08:00 |
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regression-wally.py
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increase regression's expectations of buildroot to 246 million
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2021-12-08 07:01:22 -08:00 |
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sim-buildroot
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fix buildroot graphical sim
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2021-10-31 18:33:43 -07:00 |
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sim-buildroot-batch
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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sim-coremark-batch
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Added coremark scripts to regression directory
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2021-12-01 09:08:06 -08:00 |
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sim-fp64
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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sim-fp64-batch
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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sim-wally
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Changes for floating point sims
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2021-10-27 10:37:35 -07:00 |
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sim-wally-batch
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CoreMark testing
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2021-11-18 16:14:25 -08:00 |
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wally-buildroot-batch.do
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change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros
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2021-10-25 12:25:32 -07:00 |
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wally-buildroot.do
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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wally-coremark.do
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Updated coremark testbench with the extra ports from FPGA merge.
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2021-12-08 13:40:32 -06:00 |
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wally-fp64-batch.do
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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wally-fp64.do
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Update to fpdivsqrt to go on posedge as it should. Also an update to
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2021-10-13 17:14:42 -05:00 |
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wally-pipelined-batch.do
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update scripts for handling src/*/* subdirectories
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2021-10-23 08:54:29 -07:00 |
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wally-pipelined-fpga.do
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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wally-pipelined.do
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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wave-all.do
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renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
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2021-11-17 10:53:17 -08:00 |
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wave.do
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
