forked from Github_Repos/cvw
98 lines
3.4 KiB
Systemverilog
98 lines
3.4 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtqsel4cmp.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Comparator-based Radix 4 Quotient Digit Selection
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtqsel4cmp (
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input logic [2:0] Dmsbs,
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input logic [4:0] Smsbs,
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input logic [7:0] WSmsbs, WCmsbs,
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input logic SqrtE, j1, OTFCSwapE, MDUE,
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output logic [3:0] udigit
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);
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logic [6:0] Wmsbs;
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logic [7:0] PreWmsbs;
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logic [2:0] A;
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logic [3:0] udigitsel, udigitswap;
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assign PreWmsbs = WCmsbs + WSmsbs;
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assign Wmsbs = PreWmsbs[7:1];
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// D = 0001.xxx...
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// Dmsbs = | |
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// W = xxxx.xxx...
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// Wmsbs = | |
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logic [6:0] mk2, mk1, mk0, mkm1;
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logic [6:0] mks2[7:0], mks1[7:0];
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// Prepopulate table of mks0
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assign mks2[0] = 12;
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assign mks2[1] = 14;
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assign mks2[2] = 16;
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assign mks2[3] = 17;
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assign mks2[4] = 18;
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assign mks2[5] = 20;
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assign mks2[6] = 22;
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assign mks2[7] = 23;
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assign mks1[0] = 4;
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assign mks1[1] = 4;
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assign mks1[2] = 6;
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assign mks1[3] = 6;
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assign mks1[4] = 6;
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assign mks1[5] = 8; // is the logic any cheaper if this is a 6?
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assign mks1[6] = 8;
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assign mks1[7] = 8;
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// Choose A for current operation
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always_comb
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if (SqrtE & ~MDUE) begin
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if (j1) A = 3'b101;
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else if (Smsbs == 5'b10000) A = 3'b111;
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else A = Smsbs[2:0];
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end else A = Dmsbs;
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// Choose selection constants based on a
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assign mk2 = mks2[A];
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assign mk1 = mks1[A];
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assign mk0 = -mks1[A];
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assign mkm1 = (A == 3'b000) ? -13 : -mks2[A]; // asymmetry in table
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// Compare residual W to selection constants to choose digit
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always_comb
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if ($signed(Wmsbs) >= $signed(mk2)) udigitsel = 4'b1000; // choose 2
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else if ($signed(Wmsbs) >= $signed(mk1)) udigitsel = 4'b0100; // choose 1
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else if ($signed(Wmsbs) >= $signed(mk0)) udigitsel = 4'b0000; // choose 0
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else if ($signed(Wmsbs) >= $signed(mkm1)) udigitsel = 4'b0010; // choose -1
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else udigitsel = 4'b0001; // choose -2
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assign udigitswap = {udigitsel[0], udigitsel[1], udigitsel[2], udigitsel[3]};
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assign udigit = OTFCSwapE ? udigitswap : udigitsel;
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endmodule
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