4 Commits

Author	SHA1	Message	Date
cturek	c3fdc0ab23	Renamed signals to E and M stages, forwarded preprocessed n to fsm	2022-12-22 00:43:27 +00:00
Alessandro Maiuolo	2989782fe6	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
cturek	b137a95a35	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
David Harris	6092ca757a	New fdivsqrtqsel4cmp module based on comparators rather than table lookup	2022-10-09 04:47:44 -07:00