Ross Thompson f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-04-16 14:59:03 -05:00
..
csr.sv	WFI should set EPC to PC+4	2022-04-14 17:05:22 +00:00
csrc.sv	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
csri.sv	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
csrm.sv	Added wave config	2022-04-01 12:44:14 -05:00
csrs.sv	Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.	2022-02-15 19:20:41 +00:00
csrsr.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-16 14:59:03 -05:00
csru.sv	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
privdec.sv	Cleaned warning on HPTW default state	2022-02-16 17:40:13 +00:00
privileged.sv	WFI should set EPC to PC+4	2022-04-14 17:05:22 +00:00
trap.sv	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00