Ross Thompson f8bdb6db49 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-04-16 14:59:03 -05:00
..
cache	Hacky fix to prevent ITLBMissF and TrapM bug.	2022-04-12 17:56:23 -05:00
ebu	Started make allsynth to try many experiments	2022-02-17 17:57:02 +00:00
fma	Added SystemVerilog flag to fma.do so that fma16 compiles properly	2022-03-31 17:00:38 +00:00
fpu	fixed errors and warnings in rv32e	2022-04-07 17:21:20 +00:00
generic	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
hazard	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
ieu	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
ifu	Added WFI support to IFU to keep it in the pipeline	2022-04-14 17:26:17 +00:00
lsu	Fixed possible bugs in LRSC.	2022-04-16 14:45:31 -05:00
mmu	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
muldiv	Better solution to the integer divider interrupt interaction.	2022-01-12 14:22:18 -06:00
privileged	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-16 14:59:03 -05:00
uncore	UART and clock speed changes to support 30Mhz.	2022-04-12 17:56:36 -05:00
wally	Added more ILA signals.	2022-04-02 16:39:45 -05:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00