Ross Thompson 3f62a64056 Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.		2021-12-20 23:45:55 -06:00
..
cache	Fixed bug on icache spill. if the cpu stalled on the completion it was possible to use the wrong address for the sram read. Also miss spill hit always selected the wrong address.	2021-12-20 23:27:37 -06:00
ebu	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
fpu	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
generic	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
hazard	Added proper credit to Richard Davis, the author of the original sd card reader.	2021-12-12 15:05:50 -06:00
ieu	ALUControl cleanup	2021-12-19 13:53:45 -08:00
ifu	Identified bug in the IFU which selects PCNextF when InvalidateICacheM is true. If the ID is invalid PCNextF should NOT be PCE.	2021-12-20 23:45:55 -06:00
lsu	Fixed Type 5b interaction between dcache and hptw.	2021-12-20 18:33:31 -06:00
mmu	Fixed Type 5b interaction between dcache and hptw.	2021-12-20 18:33:31 -06:00
muldiv	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
privileged	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-12-20 21:09:20 -08:00
sdc	Moved generate statements for optional units into wallypipelinedhart	2021-12-19 16:53:41 -08:00
uncore	Oups missed files in the last commit.	2021-12-15 10:25:08 -06:00
wally	Moved generate of conditional units to hart	2021-12-19 17:03:57 -08:00