forked from Github_Repos/cvw
0d260accb4
It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected
56 lines
2.2 KiB
Plaintext
56 lines
2.2 KiB
Plaintext
#--showoverrides
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#--showcommands
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# Core settings
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--override cpu/unaligned=F
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--override cpu/ignore_non_leaf_DAU=1
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--override cpu/wfi_is_nop=T
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--override cpu/mimpid=0x100
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--override cpu/misa_Extensions_mask=0x0
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# THIS NEEDS FIXING to 16
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--override cpu/PMP_registers=0
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# PMA Settings
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# 'r': read access allowed
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# 'w': write access allowed
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# 'x': execute access allowed
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# 'a': aligned access required
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# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
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# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
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# '1': 1-byte accesses allowed
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# '2': 2-byte accesses allowed
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# '4': 4-byte accesses allowed
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# '8': 8-byte accesses allowed
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# '-', space: ignored (use for input string formatting).
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#
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# SV39 Memory 0x0000000000 0x7FFFFFFFFF
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#
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--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- "; # INITIAL
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--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 "; # BOOTROM
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--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 "; # SDC
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--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 "; # CLINT
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--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- "; # PLIC
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--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- "; # UART0 error - 0x10000000 - 0x100000FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- "; # GPIO error - 0x10006000 - 0x100060FF
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 "; # UNCORE_RAM
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# Enable the Imperas instruction coverage
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#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/extensions=RV32I
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# Add Imperas simulator application instruction tracing
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--override cpu/show_c_prefix=T
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--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange
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# Exceptions and pagetables debug
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--override cpu/debugflags=6
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# Turn on verbose output for Imperas simulator and Model
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--verbose
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--override cpu/verbose=1
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# Store simulator output to logfile
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--output imperas.log
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