11 Commits

Author	SHA1	Message	Date
eroom1966	0d260accb4	Fix MISA RO and UART addresses ... It appears on inspection that the MISA register is read only in Wally In which case this has now also been set in the ImperasDV representation Also the Addresss for the UART R/W privileges are corrected	2023-03-13 11:07:19 +00:00
eroom1966	8e657c335e	Enhancements to support the PMA ranges	2023-03-10 14:09:22 +00:00
eroom1966	68f3e31547	Add support for setting PMP registers ... Add support for async DV	2023-03-08 12:44:53 +00:00
eroom1966	1169567219	fix the memory map privileges in the REF model view	2023-03-02 15:25:27 +00:00
eroom1966	72b92e8c0d	update testbench for memory privileges ... also update configuration to define value of mimpid	2023-03-01 15:37:11 +00:00
eroom1966	0ac99d2233	add files to support coverage	2023-02-15 11:13:50 +00:00
Ross Thompson	0fa89ed844	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-06 16:35:20 -06:00
eroom1966	8705df1136	remove leading space	2023-02-06 14:01:05 +00:00
eroom1966	02b4f9c304	remerge changes	2023-02-06 13:43:12 +00:00
Ross Thompson	9c5c041122	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-04 11:28:26 -06:00
David Harris	8078cafa27	Renamed regression to sim	2023-02-02 14:48:23 -08:00