bbracker cd469035be make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset		2021-07-19 15:13:03 -04:00
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ahb-muldiv.do
ahb-waves.do
cache-waves.do
default-waves.do
linux-waves.do
peripheral-waves.do