cvw/wally-pipelined/regression
Ross Thompson 7497422667 Changed several things.
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
..
old
slack-notifier
wave-dos
fpga-wave.do Changed several things. 2021-11-12 11:13:50 -06:00
linux-wave.do
regression-wally.py
sim-buildroot
sim-buildroot-batch
sim-fp64
sim-fp64-batch
sim-wally
sim-wally-batch
wally-buildroot-batch.do
wally-buildroot.do
wally-fp64-batch.do
wally-fp64.do
wally-pipelined-batch.do
wally-pipelined-fpga.do
wally-pipelined.do
wave-all.do
wave.do