forked from Github_Repos/cvw
61 lines
2.6 KiB
Systemverilog
61 lines
2.6 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: Leading Zero Anticipator
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
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input logic [WIDTH-1:0] A, // addend
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input logic [2*`NF+3:0] Pm, // product
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input logic Cin, // carry in
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input logic sub,
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output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result
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);
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logic [WIDTH:0] F;
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logic [WIDTH-1:0] B, P, G, K;
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logic [WIDTH-1:0] Pp1, Gm1, Km1;
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assign B = {{(`NF+2){1'b0}}, Pm}; // Zero extend product
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assign P = A^B;
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assign G = A&B;
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assign K= ~A&~B;
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assign Pp1 = {sub, P[WIDTH-1:1]};
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assign Gm1 = {G[WIDTH-2:0], Cin};
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assign Km1 = {K[WIDTH-2:0], ~Cin};
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// Apply function to determine Leading pattern
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// - note: the paper linked above uses the numbering system where 0 is the most significant bit
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assign F[WIDTH] = ~sub&P[WIDTH-1];
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assign F[WIDTH-1:0] = (Pp1&(G&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | G&~Gm1));
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lzc #(WIDTH+1) lzc (.num(F), .ZeroCnt(SCnt));
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endmodule
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