Ross Thompson 403daecc8e Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults. ... The defaults are used for synthesis. rv64i and rv32i: DTIM 2KiB, IROM 2KiB rv32ic: DTIM 4KiB, IROM 16KiB Regression tests require 8MiB or larger so modelsim overrides.		2022-10-11 10:47:13 -05:00
..
slack-notifier
wave-dos
wkdir
buildrootBugFinder.py
fpga-wave.do
lint-wally
linux-wave.do
make-tests.sh
Makefile
makefile-memfile
regression-wally
sim-buildroot	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
sim-buildroot-batch
sim-testfloat
sim-testfloat-batch
sim-wally
sim-wally-batch
testfloat.do
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
wally-pipelined.do	Modified the do scripts to change the DTIM_RANGE and IROM_RANGE to large values from the defaults.	2022-10-11 10:47:13 -05:00
wave-all.do
wave-fpu.do
wave.do