forked from Github_Repos/cvw
93 lines
3.4 KiB
Systemverilog
93 lines
3.4 KiB
Systemverilog
///////////////////////////////////////////
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// 1 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Basic sram with 1 read write port.
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// When clk rises Addr and CacheWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic [$clog2(DEPTH)-1:0] Adr,
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input logic [WIDTH-1:0] CacheWriteData,
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input logic WriteEnable,
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input logic [(WIDTH-1)/8:0] ByteMask,
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output logic [WIDTH-1:0] ReadData);
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logic [WIDTH-1:0] StoredData[DEPTH-1:0];
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logic [$clog2(DEPTH)-1:0] AdrD;
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logic WriteEnableD;
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localparam WM8 = WIDTH%8;
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always_ff @(posedge clk) AdrD <= Adr;
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integer index;
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/* -----\/----- EXCLUDED -----\/-----
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for(index = 0; index < WIDTH/8; index++) begin
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always_ff @(posedge clk) begin
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if (WriteEnable & ByteMask[index]) begin
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StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index];
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end
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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always_ff @(posedge clk) begin
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if (WriteEnable) begin
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for(index = 0; index < WIDTH/8; index++) begin
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if(ByteMask[index]) begin
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StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8];
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end
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end
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if (WM8 > 0) begin
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if (ByteMask[WIDTH/8]) begin
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StoredData[Adr][WIDTH-1:WIDTH-WM8] <= #1
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CacheWriteData[WIDTH-1:WIDTH-WM8];
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end
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end
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end
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end
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/* // if not a multiple of 8, MSByte is not 8 bits long.
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if(WIDTH%8 != 0) begin
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always_ff @(posedge clk) begin
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if (WriteEnable & ByteMask[WIDTH/8]) begin
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StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8];
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end
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end
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end */
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assign ReadData = StoredData[AdrD];
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endmodule
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