6 Commits

Author	SHA1	Message	Date
David Harris	0df73d203b	Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.	2022-05-03 03:45:41 -07:00
Ross Thompson	0a5b500aca	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
Ross Thompson	6d914def08	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	63b1ea88c9	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	7a129c75cd	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	32eee5a06a	More cache cleanup.	2022-02-10 10:43:37 -06:00