forked from Github_Repos/cvw
169 lines
6.5 KiB
Systemverilog
169 lines
6.5 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtpreproc.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtpreproc (
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input logic clk,
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input logic IFDivStartE,
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input logic [`NF:0] Xm, Ym,
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input logic [`NE-1:0] Xe, Ye,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic XZero,
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input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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input logic [2:0] Funct3E, Funct3M,
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input logic MDUE, W64E,
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output logic [`DIVBLEN:0] n, m,
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output logic OTFCSwap, ALTBM, BZero, As,
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output logic [`NE+1:0] QeM,
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output logic [`DIVb+3:0] X,
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output logic [`DIVb-1:0] DPreproc
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);
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logic [`DIVb-1:0] XPreproc;
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logic [`DIVb:0] SqrtX;
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logic [`DIVb+3:0] DivX;
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logic [`NE+1:0] QeE;
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// Intdiv signals
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD;
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logic [`XLEN-1:0] PosA, PosB;
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logic Bs, CalcOTFCSwap, ALTBE;
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logic [`XLEN-1:0] A64, B64;
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logic [`DIVBLEN:0] Calcn, Calcm;
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logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
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logic [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
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logic [`LOGRK-1:0] pPrTrunc;
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logic [`DIVb+3:0] PreShiftX;
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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assign As = ForwardedSrcAE[`XLEN-1] & ~Funct3E[0];
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assign Bs = ForwardedSrcBE[`XLEN-1] & ~Funct3E[0];
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assign A64 = W64E ? {{(`XLEN-32){As}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;
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assign B64 = W64E ? {{(`XLEN-32){Bs}}, ForwardedSrcBE[31:0]} : ForwardedSrcBE;
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assign CalcOTFCSwap = (As ^ Bs) & MDUE;
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assign PosA = As ? -A64 : A64;
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assign PosB = Bs ? -B64 : B64;
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assign BZero = |ForwardedSrcBE;
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assign IFNormLenX = MDUE ? {PosA, {(`DIVb-`XLEN){1'b0}}} : {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = MDUE ? {PosB, {(`DIVb-`XLEN){1'b0}}} : {Ym, {(`DIVb-`NF-1){1'b0}}};
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lzc #(`DIVb) lzcX (IFNormLenX, ell);
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lzc #(`DIVb) lzcY (IFNormLenD, Calcm);
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, ~MDUE}); // had issue with (`DIVBLEN+1)'(~MDUE) so using this instead
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assign DPreproc = IFNormLenD << (Calcm + {{`DIVBLEN{1'b0}}, ~MDUE});
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assign ZeroDiff = Calcm - ell;
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assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
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assign p = ALTBE ? '0 : ZeroDiff;
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assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
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assign pPrTrunc = pPlusr[`LOGRK-1:0];
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assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
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assign Calcn = (pPrCeil << `LOGK) - 1;
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assign IntBits = (`DIVBLEN)'(`RK) + p;
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assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
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assign SqrtX = (Xe[0]^ell[0]) ? {1'b0, ~XZero, XPreproc[`DIVb-1:1]} : {~XZero, XPreproc}; // Bottom bit of XPreproc is always zero because DIVb is larger than XLEN and NF
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assign DivX = {3'b000, ~XZero, XPreproc};
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// *** explain why X is shifted between radices (initial assignment of WS=RX)
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if (`RADIX == 2) assign PreShiftX = Sqrt ? {3'b111, SqrtX} : DivX;
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else assign PreShiftX = Sqrt ? {2'b11, SqrtX, 1'b0} : DivX;
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assign X = MDUE ? DivX >> RightShiftX : PreShiftX;
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// radix 2 radix 4
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// 1 copies DIVLEN+2 DIVLEN+2/2
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// 2 copies DIVLEN+2/2 DIVLEN+2/2*2
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// 4 copies DIVLEN+2/4 DIVLEN+2/2*4
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// 8 copies DIVLEN+2/8 DIVLEN+2/2*8
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// DIVRESLEN = DIVLEN or DIVLEN+2
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// r = 1 or 2
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// DIVRESLEN/(r*`DIVCOPIES)
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flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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flopen #(1) swapreg(clk, IFDivStartE, CalcOTFCSwap, OTFCSwap);
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flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM);
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flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, Calcn, n);
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flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, Calcm, m);
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expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .ell, .m(Calcm), .Qe(QeE));
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endmodule
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module expcalc(
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`NE-1:0] Xe, Ye,
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input logic Sqrt,
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input logic XZero,
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input logic [`DIVBLEN:0] ell, m,
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output logic [`NE+1:0] Qe
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);
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logic [`NE-2:0] Bias;
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logic [`NE+1:0] SXExp;
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logic [`NE+1:0] SExp;
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logic [`NE+1:0] DExp;
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if (`FPSIZES == 1) begin
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assign Bias = (`NE-1)'(`BIAS);
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end else if (`FPSIZES == 2) begin
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assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1);
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end else if (`FPSIZES == 3) begin
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always_comb
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case (Fmt)
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`FMT: Bias = (`NE-1)'(`BIAS);
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`FMT1: Bias = (`NE-1)'(`BIAS1);
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`FMT2: Bias = (`NE-1)'(`BIAS2);
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default: Bias = 'x;
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endcase
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end else if (`FPSIZES == 4) begin
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always_comb
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case (Fmt)
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2'h3: Bias = (`NE-1)'(`Q_BIAS);
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2'h1: Bias = (`NE-1)'(`D_BIAS);
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2'h0: Bias = (`NE-1)'(`S_BIAS);
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2'h2: Bias = (`NE-1)'(`H_BIAS);
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endcase
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end
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assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
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assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};
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// correct exponent for denormalized input's normalization shifts
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assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}};
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assign Qe = Sqrt ? SExp : DExp;
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endmodule |