| .. | 
		
		
			
			
			
			
				| slack-notifier | added instructions to slack notifier | 2022-05-18 16:50:31 -07:00 | 
		
			
			
			
			
				| wave-dos | Added generate around uncore. | 2022-08-25 10:35:24 -05:00 | 
		
			
			
			
			
				| wkdir | added wkdir in regression so regression runs out of box (assuming the old version of arch tests) | 2022-05-17 20:32:38 +00:00 | 
		
			
			
			
			
				| buildrootBugFinder.py | update to match new filesystem organization | 2022-03-26 21:28:32 +00:00 | 
		
			
			
			
			
				| fpga-wave.do | Added generate around uncore. | 2022-08-25 10:35:24 -05:00 | 
		
			
			
			
			
				| lint-wally | removed rv64fp from lint | 2022-06-21 15:48:47 -07:00 | 
		
			
			
			
			
				| linux-wave.do | Added generate around uncore. | 2022-08-25 10:35:24 -05:00 | 
		
			
			
			
			
				| make-tests.sh | simplified make-tests.sh to run the current makefile in regression | 2022-05-17 17:29:34 -07:00 | 
		
			
			
			
			
				| Makefile | More riscof makefile tuning | 2022-07-25 21:15:56 +00:00 | 
		
			
			
			
			
				| makefile-memfile | plic-s debug | 2022-08-03 12:33:09 +00:00 | 
		
			
			
			
			
				| regression-wally | Preliminary work to make DTIM and Bus compatible.  Not yet working because accesses to bus are causing illegal address faults on the bus. | 2022-08-27 20:31:09 -07:00 | 
		
			
			
			
			
				| sim-buildroot | switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv | 2022-03-01 03:11:43 +00:00 | 
		
			
			
			
			
				| sim-buildroot-batch | sim-buildroot-batch now runs wally-pipelined-batch | 2022-07-06 18:06:43 -07:00 | 
		
			
			
			
			
				| sim-testfloat | fixed error in divsqrt | 2022-07-14 18:16:00 +00:00 | 
		
			
			
			
			
				| sim-testfloat-batch | fixed error in divsqrt | 2022-07-14 18:16:00 +00:00 | 
		
			
			
			
			
				| sim-wally | Preliminary work to make DTIM and Bus compatible.  Not yet working because accesses to bus are causing illegal address faults on the bus. | 2022-08-27 20:31:09 -07:00 | 
		
			
			
			
			
				| sim-wally-batch | Fixed address decoder hanging buildroot | 2022-08-26 22:01:25 -07:00 | 
		
			
			
			
			
				| testfloat.do | srt divider merged into fpu | 2022-07-07 16:01:33 -07:00 | 
		
			
			
			
			
				| wally-harvard.do | Added support for logic memory in the IFU and LSU.  This disables the bus interface.  Peripherals do not work.  Also requires using testbench-harvard.sv.  I hope to merge this testbench with the main testbench.sv soon. | 2022-01-13 22:21:43 -06:00 | 
		
			
			
			
			
				| wally-pipelined-batch.do | Fixed address decoder hanging buildroot | 2022-08-26 22:01:25 -07:00 | 
		
			
			
			
			
				| wally-pipelined.do | Temporary commit. | 2022-08-30 15:40:42 -05:00 | 
		
			
			
			
			
				| wave-all.do | Added generate around uncore. | 2022-08-25 10:35:24 -05:00 | 
		
			
			
			
			
				| wave-fpu.do | Separated out radix 2 and radix 4 stages into different modules | 2022-08-29 04:26:14 -07:00 | 
		
			
			
			
			
				| wave.do | Maybe fixed it? | 2022-08-30 18:08:34 -05:00 |