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  • 9fdb1d3cc9 setup so the sdc does not need to load a model in the imperas test bench. Ross Thompson 2021-09-24 11:30:52 -0500
  • c644e940c2 Updated Imperas test bench to work with the SDC reader. Ross Thompson 2021-09-24 11:22:54 -0500
  • fea439b84d SDC to ABHLite interface partially done. Added SDC to adrdec and uncore. Ross Thompson 2021-09-24 10:45:09 -0500
  • 92ea88c57b Added clock gater and divider to generate the SDCCLK. Ross Thompson 2021-09-23 17:58:50 -0500
  • 3cbbd15763 Partial implementation of SDC AHBLite interface. Ross Thompson 2021-09-23 17:45:45 -0500
  • 3473f1e612 Started the AHBLite to SDC interface. Ross Thompson 2021-09-22 18:08:38 -0500
  • 3f96ff0ac0 switch testbench-linux's interrupts from xcause to mip and improve warning messages bbracker 2021-09-22 12:33:11 -0400
  • 8b97f8154f update setup scripts to new testvector files bbracker 2021-09-22 12:31:10 -0400
  • a7be88a43b Changes to make fpga synthesizable. Added preload to test simple program on wally in fpga. Ross Thompson 2021-09-22 10:54:13 -0500
  • ec0d2bc7d7 Initial SD Card reader. Ross Thompson 2021-09-22 10:50:29 -0500
  • 523d25ee7b Merge branch 'ppa' into main kipmacsaigoren 2021-09-20 01:01:47 -0500
  • 221dbe92b2 Fixed the amo on dcache miss cpu stall issue. Ross Thompson 2021-09-17 22:15:03 -0500
  • e16c27225b Finished adding the d cache flush. Required ensuring the write data, address, and size are correct when transmitting to AHBLite interface. Ross Thompson 2021-09-17 13:03:04 -0500
  • 4de4774a71 more input changes on prioirty thermometer. passes lint Kip Macsai-Goren 2021-09-17 13:07:21 -0400
  • cc4ad218cb added new fun ways of putting inputs into the priority thermometer kipmacsaigoren 2021-09-17 12:00:38 -0500
  • cfd522da6b The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted. Ross Thompson 2021-09-17 10:33:57 -0500
  • 0b1e59d075 Updated Dcache to fully support flush. This appears to work. Updated PCNextF so it points to the correct PC after icache invalidate. Build root crashes with PCW mismatch and invalid register writes. Ross Thompson 2021-09-17 10:25:21 -0500
  • 615fd41e7b Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes. Ross Thompson 2021-09-16 18:32:29 -0500
  • 348187ea70 Added counters to walk through d cache flush. Ross Thompson 2021-09-16 17:12:51 -0500
  • d901f60a6d Added flush controls to cachway. Ross Thompson 2021-09-16 16:56:48 -0500
  • cae350abb7 Added invalidate to icache. Ross Thompson 2021-09-16 16:15:54 -0500
  • a158558b83 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-09-15 17:31:11 -0400
  • ff5379fd95 fix regression bbracker 2021-09-15 17:30:59 -0400
  • 97c474327c changed priority circuits for synthesis and light cleanup kipmacsaigoren 2021-09-15 12:24:24 -0500
  • 2cd2fe0828 Added git things to make it all a little nicer and synthesis work. kipmacsaigoren 2021-09-15 12:15:53 -0500
  • 9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. David Harris 2021-09-15 13:14:00 -0400
  • ee1503a249 created script to determine which functions are most frequently used bbracker 2021-09-14 19:41:05 -0400
  • 2738e9c900 IRQ timing template bbracker 2021-09-13 18:48:28 -0400
  • 92385a1d51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-09-13 12:41:07 -0400
  • 9fa048980d Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64 David Harris 2021-09-13 12:40:40 -0400
  • c60edb1a04 Merge branch 'main' into fpga Ross Thompson 2021-09-13 09:45:59 -0500
  • cd6d1e0b12 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-09-13 09:41:34 -0500
  • 7be1160a48 Cleaned up wally-arch test scripts David Harris 2021-09-13 00:02:32 -0400
  • bbb6c7bef7 Restored old integer divider David Harris 2021-09-12 22:07:52 -0400
  • 296da4f437 FPGA test bench and test program. Ross Thompson 2021-09-12 20:41:54 -0500
  • dd1e7548ed Modified rxfull determination in UART, started division David Harris 2021-09-12 20:00:24 -0400
  • 3e590717c2 Removed one more genout bit. Ross Thompson 2021-09-11 18:42:47 -0500
  • 9cbc6755df Merge branch 'main' into fpga Ross Thompson 2021-09-11 16:00:23 -0500
  • 5922bae299 Added calibration input. fixed HRESP duplication. Ross Thompson 2021-09-11 15:59:27 -0500
  • be864abcc5 Fixed bug with or_rows. If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1. Ross Thompson 2021-09-11 15:51:11 -0500
  • 570aab4275 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. Ross Thompson 2021-09-11 15:40:27 -0500
  • 5744796431 Fixed dcache to prevent latches in FPGA synthesized design. Ross Thompson 2021-09-10 17:54:26 -0500
  • 1656f88871 Merge branch 'fpga' of github.com:davidharrishmc/riscv-wally into fpga Ross Thompson 2021-09-09 15:49:45 -0500
  • af74a8c5cb Third attempt at fixing the write enables for the icache cacheway. Ross Thompson 2021-09-09 15:08:10 -0500
  • 6f4542f063 Third attempt at fixing the write enables for the icache cacheway. Ross Thompson 2021-09-09 15:08:10 -0500
  • 6965bde95c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Refixed some bit width issues in the icache. Ross Thompson 2021-09-09 12:44:02 -0500
  • 1d370ca71f fixed some lint bugs. Ross Thompson 2021-09-09 12:38:57 -0500
  • 4a17af5b7c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main bbracker 2021-09-09 13:22:31 -0400
  • 3a520cb540 changed fix_mem to not use hardcoded file names bbracker 2021-09-09 13:22:24 -0400
  • 12bd351edf Lint cleaning, riscv-arch-test testing David Harris 2021-09-09 11:05:12 -0400
  • 9480f8efdb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-09-08 16:00:12 -0400
  • 118cb7fb87 Added testbench-arch for riscv-arch-test suite David Harris 2021-09-08 15:59:40 -0400
  • 86fbe2a654 Changed configs to support 4 ways set associative caches. Ross Thompson 2021-09-08 12:52:49 -0500
  • 6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-09-08 12:47:03 -0500
  • a15d6c1c96 Slight modification to wave file. Ross Thompson 2021-09-08 10:40:46 -0500
  • bb84354a47 fixed bug where M mode was sensitive to S mode traps bbracker 2021-09-07 19:14:39 -0400
  • f8272c45d1 make testbench successfully deactivate TimerIntM so as to create a nice pulse bbracker 2021-09-07 15:36:47 -0400
  • 49e75d579c Set associate icache working, but way 0 is never written. Ross Thompson 2021-09-07 12:46:16 -0500
  • da9a366d20 No longer forcing CSRReadValM because that can feedback to corrupt some CSRs bbracker 2021-09-06 22:59:54 -0400
  • 05455f8392 Changed name of memory in icache. Ross Thompson 2021-09-06 20:54:52 -0500
  • 502ddb3bb5 help in case a script is run accidentally bbracker 2021-09-06 16:23:45 -0400
  • b3bc3cf6d0 modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations) bbracker 2021-09-04 19:49:26 -0400
  • c463f177e9 restore functionality of being able to turn on waves at a certain instruction count; restore linux-waves.do because wave.do seems to be in disrepair bbracker 2021-09-04 19:45:04 -0400
  • 135404174e switching over to hopefully more consistent QEMU simulated clock bbracker 2021-09-04 19:43:39 -0400
  • 9fde9f09f2 replace triple gdb breakpoint continue with a double breakpoint ignore in hopes of improving parsing bbracker 2021-09-04 19:41:55 -0400
  • 02a1fda650 Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR James E. Stine 2021-09-03 10:26:38 -0500
  • f1a39b467d output trace to linux-testvectors folder bbracker 2021-09-01 17:37:46 -0400
  • 2968623f9a Partial multiway set associative icache. Ross Thompson 2021-08-30 10:49:24 -0500
  • 70f332fe2f FMA cleanup Katherine Parry 2021-08-28 10:53:35 -0400
  • 6a9fa2fae3 Fixed bugs I introduced to the icache. Ross Thompson 2021-08-27 15:00:40 -0500
  • d433db3048 Renamed PCMux (icache) to SelAdr to match dcache. Removed unused cache files. Ross Thompson 2021-08-27 11:14:10 -0500
  • 96cbd8e785 Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm. One downside is it increases the icache complexity. However it also fixes an untested bug. If a region was uncacheable it would have been possible for the request to be made multiple times. Now that is not possible. Additionally spills were oscillating between the spill hit states without this change. The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits. Ross Thompson 2021-08-27 11:03:36 -0500
  • 4ace7fe946 Renamed ICacheCntrl to icachefsm. Ross Thompson 2021-08-26 15:57:17 -0500
  • d6ff89b7e6 Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits. Ross Thompson 2021-08-26 15:43:02 -0500
  • aea7afead6 Finished moving data path logic from the ICacheCntrl.sv to icache.sv. Ross Thompson 2021-08-26 13:00:21 -0500
  • 86fc632790 Moved data path logic from icacheCntrl to icache. Ross Thompson 2021-08-26 10:58:19 -0500
  • fd28c4f556 Removed unused logic in icache. Ross Thompson 2021-08-26 10:49:54 -0500
  • e4bbd3bbc7 Converted the icache type from logic to state type. Ross Thompson 2021-08-26 10:41:42 -0500
  • 91fba80a6d Additional cleanup of ahblite. Ross Thompson 2021-08-25 22:53:20 -0500
  • 8836d91896 Removed amo logic from ahblite. Removed many unused signals from ahblite. Ross Thompson 2021-08-25 22:45:13 -0500
  • 596bc138bc Forgot to include a few files in the last few commits. Also reorganized the dcache by read cpu path, write cpu path, and bus interface path. Changed i/o names on subwordread to match signals in dcache. Ross Thompson 2021-08-25 22:30:05 -0500
  • 0530047f53 Moved dcache fsm to separate module. Ross Thompson 2021-08-25 21:37:10 -0500
  • d23b860c96 Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory. This was correct for the LRU but incorrect for the data, tag, valid, and dirty storage. Ross Thompson 2021-08-25 21:09:42 -0500
  • c5e2443298 Replaced dcache generate ORing with or_rows. Ross Thompson 2021-08-25 13:46:36 -0500
  • e5336f4ee1 Rename of DCacheMem to cacheway. simplified dcache names. Ross Thompson 2021-08-25 13:33:15 -0500
  • e9a1dc90f6 Removed generate around the dcache memories. Ross Thompson 2021-08-25 13:27:26 -0500
  • 2ccf479354 Moved more logic inside the dcache memory. Ross Thompson 2021-08-25 13:17:07 -0500
  • 35e57a7c61 partial dcache reorg. Ross Thompson 2021-08-25 12:42:05 -0500
  • 983524e81b Updated linux test bench documenation and scripts. Ross Thompson 2021-08-25 10:54:47 -0500
  • 7d24ed3c51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main David Harris 2021-08-25 06:47:20 -0400
  • 3fa55a01f4 simplified or_rows generation and renamed oneHotDecoder to onehotdecoder David Harris 2021-08-25 06:46:41 -0400
  • fe378f2692 Added function tracking to linux test bench. Ross Thompson 2021-08-24 11:08:46 -0500
  • 0cc47f3daf Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. Ross Thompson 2021-08-23 15:43:43 -0500
  • c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. InstrValidM was used to control when the counter was updated. However this is not suppress the counter when the instruction is flushed in the M stage. Ross Thompson 2021-08-23 12:24:03 -0500
  • 9fdcc6c9ca Renamed output of qemu trace. Ross Thompson 2021-08-22 22:56:34 -0500
  • 2825074114 Confirmed David's changes to the interrupt code. When a timer interrupt occurs it should be routed to the machine interrupt pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is Machine. This is true for all the interrupts. The interrupt should not be masked even though it is delegated to a lower privilege. Since the CPU is currently in machine mode the interrupt must be taken if MIE. Ross Thompson 2021-08-22 21:35:59 -0500
  • 4677b4bb38 possible interrupt code David Harris 2021-08-22 17:02:40 -0400
  • ddbc659d7b Fixed bug with coremark do file. When I moved the testbench to have a common set of files i forgot to remove the old path reference to function_radix.sv in wally-coremark_bare.do. Ross Thompson 2021-08-19 10:33:11 -0500
  • 65870877c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main Ross Thompson 2021-08-17 16:06:54 -0500
  • 91b51c698e Minor changes to dcache. Ross Thompson 2021-08-17 15:22:10 -0500