slmnemo
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bfa500234d
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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cturek
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c170a8d9b6
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Changed testbench to operate on two inputs and one output, changed all test generators, changed srt module to return only one output and take in Mod as a signal to compute integer remainder
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2022-07-22 01:27:08 +00:00 |
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cturek
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abe1ff906e
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Renamed variables, moved output handling to postprocessor, added remainder handling
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2022-07-21 20:45:08 +00:00 |
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Daniel Torres
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a17361870f
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 12:50:04 -07:00 |
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Daniel Torres
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d44ec059d0
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made makefile more specific, just incase future additions
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2022-07-21 12:50:02 -07:00 |
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Daniel Torres
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6e9b4f4075
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removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
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2022-07-21 12:47:51 -07:00 |
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Katherine Parry
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e330a840b0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-21 19:38:15 +00:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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cturek
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ddc237f6bc
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Division working too
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2022-07-21 17:59:10 +00:00 |
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cturek
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9c694b887e
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Updated Radix2 Sqrt to follow new algorithm
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2022-07-21 17:36:21 +00:00 |
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Daniel Torres
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dad913cb82
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fixed gitmodules
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2022-07-21 10:15:13 -07:00 |
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Daniel Torres
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f33c6c9455
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-21 10:14:20 -07:00 |
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Daniel Torres
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e9aedfdc53
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changed the default branch of embench
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2022-07-21 10:14:05 -07:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Katherine Parry
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e8c9830b88
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turn off 2 word store durring non-fp instructions
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2022-07-20 21:57:23 +00:00 |
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Ross Thompson
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9868e685a4
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Katherine Parry
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fb890d621d
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moved ctrl signal registers into fctrl, also a lot of code cleaning
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2022-07-20 02:27:39 +00:00 |
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cturek
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d7e90a7086
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divsqrt working for floating point
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2022-07-20 02:04:20 +00:00 |
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cturek
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f75d1c2eef
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-20 02:00:50 +00:00 |
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cturek
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8e66b81821
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New radix-2 algorithm implemented and working
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2022-07-20 02:00:43 +00:00 |
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David Harris
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9d125addfa
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-20 01:49:36 +00:00 |
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David Harris
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4c740e1494
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Reordered embench Makefile to run size tests first
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2022-07-20 01:49:33 +00:00 |
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cturek
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db39a05abc
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small changes
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2022-07-20 01:36:25 +00:00 |
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Katherine Parry
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531829f7c8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-19 23:44:41 +00:00 |
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Katherine Parry
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afcddf7035
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oprimized zeros and replaced complex ?: with always_comb
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2022-07-19 23:44:37 +00:00 |
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Daniel Torres
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7632ce9ee9
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embench no longer launches run automatiacally, need to use make run
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2022-07-19 15:16:12 -07:00 |
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Daniel Torres
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d33d0d22bd
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commented out embench 2.0 tests
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2022-07-19 13:36:18 -07:00 |
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Daniel Torres
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2c2c8d4d9b
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made changes to makefile, now builds fastest version (RV64im) by default. Also removed redundent CFLAG funroll-all-loops (was duplicated)
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2022-07-19 13:17:02 -07:00 |
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slmnemo
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77f7b179ee
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fixed GPIO test by adding a new function to clear PLIC interrupts
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2022-07-19 08:59:16 -07:00 |
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Ross Thompson
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ffda64587c
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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David Harris
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38fac8e05c
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-19 02:58:13 +00:00 |
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David Harris
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8caab918ec
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Removed duplicate -march from CoreMark makefile
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2022-07-19 02:58:07 +00:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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a590728350
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reworked fmashiftcalc to match book
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2022-07-19 00:04:24 +00:00 |
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David Harris
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6ec2a5db4a
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Coremark cleanup
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2022-07-18 16:48:13 -07:00 |
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David Harris
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59eb11b73a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 23:11:12 +00:00 |
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David Harris
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ab08826b6a
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Cleaned up Coremark makefile
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2022-07-18 23:10:22 +00:00 |
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Katherine Parry
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86f0327f79
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 20:49:01 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Daniel Torres
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a190bc4471
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-18 13:30:50 -07:00 |
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Daniel Torres
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877d0b7364
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added additional changes to coremark to support rv32
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2022-07-18 13:30:35 -07:00 |
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Daniel Torres
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c65aa54a1e
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-07-18 12:13:48 -07:00 |
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Daniel Torres
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3f5a5e1093
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added the sail change to spike to let it all run normally
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2022-07-18 12:13:15 -07:00 |
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Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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ea7b32a50b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 17:31:29 +00:00 |
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Katherine Parry
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5bb1478859
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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David Harris
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f4c1c867d0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 10:19:20 +00:00 |
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Ross Thompson
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a88543275f
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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3670c47141
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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