David Harris
fb5ddc476c
Removed CountEn
2022-08-25 18:05:44 -07:00
David Harris
7eae6765df
Removed wordcount
2022-08-25 18:04:49 -07:00
David Harris
73419f0d41
Added buscachefsm for system with bus and cache
2022-08-25 18:01:01 -07:00
David Harris
b96942e84c
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
David Harris
5b3c68fe74
ahblite cleanup
2022-08-25 12:44:25 -07:00
David Harris
d7be94fab2
Cleaned up SelBusWord
2022-08-25 11:18:13 -07:00
David Harris
7a129af9ad
Removed M sufix from busdp signals
2022-08-25 11:13:01 -07:00
David Harris
78618f5fc0
Renaming LSU signals from busdp
2022-08-25 11:05:10 -07:00
David Harris
89860588b8
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
David Harris
4ecdbb308a
Renamed DCache to Cache in busdp/busfsm signal interface
2022-08-25 06:21:22 -07:00
David Harris
cb2c0fe027
Minor name cleanups
2022-08-25 04:28:25 -07:00
Ross Thompson
ee3d968da0
Found small bug in busfsm which was issuing 1 extra memory read after each cache line fetch. Does not appear to have translated to an extra read out of ahblite.
2022-08-23 18:51:11 -05:00
David Harris
a9a5285ba8
Named HTRANS states in busfsm
2022-08-22 13:56:46 -07:00
Ross Thompson
970a90dd72
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
334008630f
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
slmnemo
98c07ce2c0
Added more comments
2022-06-13 12:26:08 -07:00
slmnemo
3d715a098c
Added comment about name of LSUBusInit/Lock signal
2022-06-13 10:56:02 -07:00
slmnemo
cadd62e49f
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
2022-06-10 20:43:56 -07:00
slmnemo
beb4317e68
Added comments to signals added so the bus is easier to analyze
2022-06-10 20:30:04 -07:00
slmnemo
b7357efc6b
Fixed failed regression state by only enabling counting when doing cached operations
2022-06-10 20:00:09 -07:00
slmnemo
63ed390c90
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
2022-06-10 19:10:01 -07:00
slmnemo
dc11066ff2
Passed Regression: Seems to work perfectly fine
2022-06-09 18:21:13 -07:00
slmnemo
3e8d3bae88
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
0d04751c77
Fixed error when doing uncached accesses where HTRANS was always 2
2022-06-08 18:58:07 -07:00
slmnemo
81d373c7ab
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
2022-06-08 17:34:02 -07:00
slmnemo
315c2f0669
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
2d76953d42
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
73e0c1c07f
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
slmnemo
446ad498aa
Fixed double assignment on LSUBurstType
2022-06-01 01:04:49 +00:00
slmnemo
bc17f883d4
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
2022-05-26 18:41:27 -07:00
slmnemo
847c7930c4
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
Ross Thompson
70e207e010
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
59f04f2518
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
fdb4f909fc
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
f4e62bcb54
Cleanup busdp.
2022-01-31 12:17:07 -06:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
