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f6e8e45901
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61 Commits

Author SHA1 Message Date
James E. Stine
f6e8e45901 Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking 2021-10-22 13:41:50 -05:00
James E. Stine
dd7dbaa382 Clean up some FPU and add pipelined fpdivsqrt to fpu.sv 2021-10-21 13:52:12 -05:00
James E. Stine
c5b99300e7 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
James E. Stine
1dba57dce7 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
Katherine Parry
539d21645f some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
bbracker
90ccd60790 simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
Katherine Parry
77fe00947e FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
James E. Stine
a91c0c8fc7 Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat 2021-10-06 08:26:09 -05:00
Katherine Parry
70f332fe2f FMA cleanup 2021-08-28 10:53:35 -04:00
Katherine Parry
c8847b27e8 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Katherine Parry
aedd71d570 move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Katherine Parry
e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Katherine Parry
d60e394ef9 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Katherine Parry
ef28679721 fpu cleanup 2021-07-24 14:59:57 -04:00
David Harris
63718cef8f Move Z=0 mux out of unpacker. 2021-07-22 14:22:28 -04:00
David Harris
21a65f45cd Partial work on Unpacking exponents to larger word size. FCVT and FMA are presently broken. 2021-07-22 14:18:27 -04:00
David Harris
44141047ef Removed Assumed1 from FPU interface 2021-07-22 13:04:47 -04:00
David Harris
3ad2170ffd Simplified interface to fclassify and fsgn (fixed) 2021-07-22 12:33:38 -04:00
David Harris
5e155e4fd1 Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Katherine Parry
01f0b4e5df FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
James E. Stine
12e09a7ace slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Katherine Parry
f5bfdf46db fpu unpacking unit created 2021-07-14 17:56:49 -04:00
James E. Stine
46001fef27 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Katherine Parry
f3ac46df86 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
ac163e091c Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
Katherine Parry
30ff212ca8 FPU update 2021-07-02 12:40:58 -04:00
Katherine Parry
0c2b7a1132 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Katherine Parry
7e3483b283 FPU forwarding reworked pt.1 2021-06-24 18:39:18 -04:00
Katherine Parry
8eed89616c fpu clean-up 2021-06-23 16:42:40 -04:00
Katherine Parry
353a27f12f rv64f FLW passes imperas tests 2021-06-22 16:36:16 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
Katherine Parry
4177f4f148 Updated FMA 2021-06-14 13:42:53 -04:00
Katherine Parry
0acf665a8b lint is clean 2021-06-07 14:22:54 -04:00
Katherine Parry
75a6097467 fixed lint warnings for fpu and lzd 2021-06-05 12:06:33 -04:00
Katherine Parry
fc65aedbd6 Double-precision FMA instructions 2021-06-04 14:00:11 -04:00
Ross Thompson
e50a1ef5e4 Fixed a few lint errors, 
clock gater was wrong,
missing signal definitions in branch predictor.
 2021-06-02 09:33:24 -05:00
James E. Stine
564d7c4adb Minor cosmetic update to fpu.sv 2021-06-01 15:45:32 -04:00
Ross Thompson
fe22fd2db8 added clock gater to floating point divider to speed up simulation time. 2021-06-01 13:46:21 -05:00
Katherine Parry
778ba6bbf5 classify unit created and passes imperas tests 2021-05-27 18:53:55 -04:00
Katherine Parry
1459d840ed All compare instructions pass imperas tests 2021-05-27 15:23:28 -04:00
Katherine Parry
309e6c3dc1 FADD and FSUB imperas tests pass 2021-05-26 12:33:33 -04:00
Katherine Parry
e7190b0690 renamed top level FPU wires 2021-05-25 20:04:34 -04:00
James E. Stine
bb5404e14a Update FPregfile to use more compact code and better structure for ease in reading 2021-05-25 13:21:59 -05:00
Katherine Parry
90d5fdba04 FMV.X.D imperas test passes 2021-05-24 14:44:30 -04:00
James E. Stine
6f38b7633c Update header for FPadd 2021-05-24 08:28:16 -05:00