forked from Github_Repos/cvw
497 lines
24 KiB
Systemverilog
Executable File
497 lines
24 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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//
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// Written:
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// Modified:
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//
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// Purpose: FPU
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module fpu (
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input logic [2:0] FRM_REGW, // Rounding mode from CSR
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input logic reset,
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input logic clk,
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] SrcAE, // Integer input being processed
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input logic [`XLEN-1:0] SrcAM, // Integer input being written into fpreg
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input logic StallE, StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic [`XLEN-1:0] ReadDataW, // Read data from memory
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input logic RegWriteD, // register write enable from ieu
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output logic [4:0] SetFflagsM, // FPU flags
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output logic [1:0] FMemRWM, // Read/write enable for memory {read, write}
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output logic FStallD, // Stall the decode stage if Div/Sqrt instruction
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output logic FWriteIntE, FWriteIntM, FWriteIntW, // Write integer register enable
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output logic [`XLEN-1:0] FWriteDataM, // Data to be written to memory
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output logic FDivBusyE, // Is the divison/sqrt unit busy
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output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
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output logic [`XLEN-1:0] FPUResultW); // FPU result
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// control logic signal instantiation
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logic FWriteEnD, FWriteEnE, FWriteEnM, FWriteEnW; // FP register write enable
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logic [2:0] FrmD, FrmE, FrmM, FrmW; // FP rounding mode
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logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double
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logic FDivStartD, FDivStartE; // Start division
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logic FWriteIntD; // Write to integer register
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logic FOutputInput2D, FOutputInput2E; // Put Input2 in Input1 if a store instruction
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logic [1:0] FMemRWD, FMemRWE; // Read and write enable for memory
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logic [1:0] FForwardInput1D, FForwardInput1E; // Input1 forwarding mux control signal
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logic [1:0] FForwardInput2D, FForwardInput2E; // Input2 forwarding mux control signal
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logic FForwardInput3D, FForwardInput3E; // Input3 forwarding mux control signal
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logic FInput2UsedD; // Is input 2 used
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logic FInput3UsedD; // Is input 3 used
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logic [2:0] FResultSelD, FResultSelE, FResultSelM, FResultSelW; // Select FP result
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logic [3:0] FOpCtrlD, FOpCtrlE, FOpCtrlM, FOpCtrlW; // Select which opperation to do in each component
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logic SelLoadInputE, SelLoadInputM; // Select which adress to load when single precision
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// regfile signals //*** KEP lint warning - changed `XLEN-1 to 63
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logic [4:0] RdE, RdM, RdW; // what adress to write to // ***Can take from ieu insted of pipelining
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logic [63:0] FWDM; // Write data for FP register
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logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage
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logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage
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logic [63:0] FInput1E, FInput1M, FInput1W, FInput1tmpE; // Input 1 to the various units (after forwarding)
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logic [63:0] FInput2E, FInput2M; // Input 2 to the various units (after forwarding)
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logic [63:0] FInput3E, FInput3M; // Input 3 to the various units (after forwarding)
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logic [63:0] FLoadResultW, FLoadStoreResultM, FLoadStoreResultW; // Result for load, store, and move to int-reg instructions
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// div/sqrt signals
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logic DivDenormE, DivDenormM, DivDenormW;
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logic DivOvEn, DivUnEn;
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logic [63:0] FDivResultE, FDivResultM, FDivResultW;
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logic [4:0] FDivFlagsE, FDivFlagsM, FDivFlagsW;
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logic FDivSqrtDoneE, FDivSqrtDoneM;
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logic [63:0] DivInput1E, DivInput2E;
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logic HoldInputs; // keep forwarded inputs arround durring division
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// FMA signals
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logic [105:0] ProdManE, ProdManM;
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logic [161:0] AlignedAddendE, AlignedAddendM;
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logic [12:0] ProdExpE, ProdExpM;
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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logic XZeroE, YZeroE, ZZeroE, XZeroM, YZeroM, ZZeroM;
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logic XInfE, YInfE, ZInfE, XInfM, YInfM, ZInfM;
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logic XNaNE, YNaNE, ZNaNE, XNaNM, YNaNM, ZNaNM;
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logic [63:0] FmaResultM, FmaResultW;
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logic [4:0] FmaFlagsM, FmaFlagsW;
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// add/cvt signals
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logic [63:0] AddSumE, AddSumTcE;
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logic [3:0] AddSelInvE;
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logic [10:0] AddExpPostSumE;
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logic AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE;
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logic AddDenormInE, AddSwapE, AddNormOvflowE, AddSignAE;
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logic AddConvertE;
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logic [63:0] AddFloat1E, AddFloat2E;
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logic [11:0] AddExp1DenormE, AddExp2DenormE;
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logic [10:0] AddExponentE;
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logic [2:0] AddRmE;
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logic [3:0] AddOpTypeE;
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logic AddPE, AddOvEnE, AddUnEnE;
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logic AddDenormM;
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logic [63:0] AddSumM, AddSumTcM;
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logic [3:0] AddSelInvM;
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logic [10:0] AddExpPostSumM;
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logic AddCorrSignM, AddOp1NormM, AddOp2NormM, AddOpANormM, AddOpBNormM, AddInvalidM;
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logic AddDenormInM, AddSwapM, AddNormOvflowM, AddSignAM;
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logic AddConvertM, AddSignM;
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logic [63:0] AddFloat1M, AddFloat2M;
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logic [11:0] AddExp1DenormM, AddExp2DenormM;
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logic [10:0] AddExponentM;
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logic [63:0] AddOp1M, AddOp2M;
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logic [2:0] AddRmM;
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logic [3:0] AddOpTypeM;
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logic AddPM, AddOvEnM, AddUnEnM;
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logic [63:0] FAddResultM, FAddResultW;
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logic [4:0] FAddFlagsM, FAddFlagsW;
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// cmp signals
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logic [7:0] WE, WM;
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logic [7:0] XE, XM;
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logic ANaNE, ANaNM;
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logic BNaNE, BNaNM;
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logic AzeroE, AzeroM;
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logic BzeroE, BzeroM;
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logic CmpInvalidM, CmpInvalidW;
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logic [1:0] CmpFCCM, CmpFCCW;
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logic [63:0] FCmpResultM, FCmpResultW;
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// fsgn signals
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logic [63:0] SgnResultE, SgnResultM, SgnResultW;
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logic [4:0] SgnFlagsE, SgnFlagsM, SgnFlagsW;
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// instantiation of W stage regfile signals
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logic [63:0] AlignedSrcAM, ForwardSrcAM, SrcAW;
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// classify signals
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logic [63:0] ClassResultE, ClassResultM, ClassResultW;
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// 64-bit FPU result
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logic [63:0] FPUResult64W, FPUResult64E;
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logic [4:0] FPUFlagsW;
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// pipeline control logic
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logic PipeEnableDE;
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logic PipeEnableEM;
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logic PipeEnableMW;
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logic PipeClearDE;
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logic PipeClearEM;
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logic PipeClearMW;
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// temporarily assign pipe clear and enable signals
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// to never flush & always be running
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localparam PipeClear = 1'b0;
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localparam PipeEnable = 1'b1;
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always_comb begin
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PipeEnableDE = ~StallE;
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PipeEnableEM = ~StallM;
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PipeEnableMW = ~StallW;
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PipeClearDE = FlushE;
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PipeClearEM = FlushM;
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PipeClearMW = FlushW;
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end
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//DECODE STAGE
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// Hazard unit for FPU
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fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
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// top-level controller for FPU
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fctrl ctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .*);
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// regfile instantiation
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FPregfile fpregfile (clk, reset, FWriteEnW,
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InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
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FPUResult64W,
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FRD1D, FRD2D, FRD3D);
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//*****************
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// fpregfile D/E pipe registers
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//*****************
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flopenrc #(64) DEReg1(clk, reset, PipeClearDE, PipeEnableDE, FRD1D, FRD1E);
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flopenrc #(64) DEReg2(clk, reset, PipeClearDE, PipeEnableDE, FRD2D, FRD2E);
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flopenrc #(64) DEReg3(clk, reset, PipeClearDE, PipeEnableDE, FRD3D, FRD3E);
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//*****************
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// other D/E pipe registers
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//*****************
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flopenrc #(1) DEReg4(clk, reset, PipeClearDE, PipeEnableDE, FWriteEnD, FWriteEnE);
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flopenrc #(3) DEReg5(clk, reset, PipeClearDE, PipeEnableDE, FResultSelD, FResultSelE);
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flopenrc #(3) DEReg6(clk, reset, PipeClearDE, PipeEnableDE, FrmD, FrmE);
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flopenrc #(1) DEReg7(clk, reset, PipeClearDE, PipeEnableDE, FmtD, FmtE);
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flopenrc #(5) DEReg8(clk, reset, PipeClearDE, PipeEnableDE, InstrD[11:7], RdE);
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flopenrc #(4) DEReg9(clk, reset, PipeClearDE, PipeEnableDE, FOpCtrlD, FOpCtrlE);
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flopenrc #(1) DEReg10(clk, reset, PipeClearDE, PipeEnableDE, FDivStartD, FDivStartE);
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flopenrc #(2) DEReg11(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput1D, FForwardInput1E);
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flopenrc #(2) DEReg12(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput2D, FForwardInput2E);
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flopenrc #(1) DEReg13(clk, reset, PipeClearDE, PipeEnableDE, FForwardInput3D, FForwardInput3E);
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flopenrc #(64) DEReg14(clk, reset, PipeClearDE, PipeEnableDE, FPUResult64W, FPUResult64E);
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flopenrc #(1) DEReg15(clk, reset, PipeClearDE, PipeEnableDE, FWriteIntD, FWriteIntE);
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flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, FOutputInput2D, FOutputInput2E);
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flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
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flopenrc #(1) DEReg18(clk, reset, PipeClearDE, PipeEnableDE, InstrD[15], SelLoadInputE);
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//EXECUTION STAGE
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// input muxs for forwarding
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mux2 #(64) SrcAMuxForward({SrcAM[31:0], 32'b0}, {SrcAM, {64-`XLEN{1'b0}}}, FmtM, ForwardSrcAM);
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mux4 #(64) FInput1Emux(FRD1E, FPUResult64W, FPUResult64E, ForwardSrcAM, FForwardInput1E, FInput1tmpE);
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mux3 #(64) FInput2Emux(FRD2E, FPUResult64W, FPUResult64E, FForwardInput2E, FInput2E);
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mux2 #(64) FInput3Emux(FRD3E, FPUResult64E, FForwardInput3E, FInput3E);
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mux2 #(64) FOutputInput2mux(FInput1tmpE, FInput2E, FOutputInput2E, FInput1E);
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// first of two-stage instance of floating-point fused multiply-add unit
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fma1 fma1 (.X(FInput1E), .Y(FInput2E), .Z(FInput3E), .FOpCtrlE(FOpCtrlE[2:0]),.*);
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// first and only instance of floating-point divider
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logic fpdivClk;
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clockgater fpdivclkg(.E(FDivStartE),
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.SE(1'b0),
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.CLK(clk),
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.ECLK(fpdivClk));
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// capture the inputs for div/sqrt
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flopenrc #(64) reg_input1 (.d(FInput1E), .q(DivInput1E),
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.en(~HoldInputs), .clear(FDivSqrtDoneE),
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.reset(reset), .clk(clk));
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flopenrc #(64) reg_input2 (.d(FInput2E), .q(DivInput2E),
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.en(~HoldInputs), .clear(FDivSqrtDoneE),
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.reset(reset), .clk(clk));
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fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .*);
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// first of two-stage instance of floating-point add/cvt unit
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fpuaddcvt1 fpadd1 (.*);
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// first of two-stage instance of floating-point comparator
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fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, FInput1E, FInput2E, FOpCtrlE[1:0]);
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// first and only instance of floating-point sign converter
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fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
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// first and only instance of floating-point classify unit
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fpuclassify fpuclass (.*);
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//*****************
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//fpregfile D/E pipe registers
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//*****************
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flopenrc #(64) EMFpReg1(clk, reset, PipeClearEM, PipeEnableEM, FInput1E, FInput1M);
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flopenrc #(64) EMFpReg2(clk, reset, PipeClearEM, PipeEnableEM, FInput2E, FInput2M);
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flopenrc #(64) EMFpReg3(clk, reset, PipeClearEM, PipeEnableEM, FInput3E, FInput3M);
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//*****************
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// fma E/M pipe registers
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//*****************
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flopenrc #(106) EMRegFma3(clk, reset, PipeClearEM, PipeEnableEM, ProdManE, ProdManM);
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flopenrc #(162) EMRegFma4(clk, reset, PipeClearEM, PipeEnableEM, AlignedAddendE, AlignedAddendM);
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flopenrc #(13) EMRegFma6(clk, reset, PipeClearEM, PipeEnableEM, ProdExpE, ProdExpM);
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flopenrc #(1) EMRegFma7(clk, reset, PipeClearEM, PipeEnableEM, AddendStickyE, AddendStickyM);
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flopenrc #(1) EMRegFma8(clk, reset, PipeClearEM, PipeEnableEM, KillProdE, KillProdM);
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flopenrc #(1) EMRegFma10(clk, reset, PipeClearEM, PipeEnableEM, XZeroE, XZeroM);
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flopenrc #(1) EMRegFma11(clk, reset, PipeClearEM, PipeEnableEM, YZeroE, YZeroM);
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flopenrc #(1) EMRegFma12(clk, reset, PipeClearEM, PipeEnableEM, ZZeroE, ZZeroM);
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flopenrc #(1) EMRegFma16(clk, reset, PipeClearEM, PipeEnableEM, XInfE, XInfM);
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flopenrc #(1) EMRegFma17(clk, reset, PipeClearEM, PipeEnableEM, YInfE, YInfM);
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flopenrc #(1) EMRegFma18(clk, reset, PipeClearEM, PipeEnableEM, ZInfE, ZInfM);
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flopenrc #(1) EMRegFma19(clk, reset, PipeClearEM, PipeEnableEM, XNaNE, XNaNM);
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flopenrc #(1) EMRegFma20(clk, reset, PipeClearEM, PipeEnableEM, YNaNE, YNaNM);
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flopenrc #(1) EMRegFma21(clk, reset, PipeClearEM, PipeEnableEM, ZNaNE, ZNaNM);
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//*****************
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// fpadd E/M pipe registers
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//*****************
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flopenrc #(64) EMRegAdd1(clk, reset, PipeClearEM, PipeEnableEM, AddSumE, AddSumM);
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flopenrc #(64) EMRegAdd2(clk, reset, PipeClearEM, PipeEnableEM, AddSumTcE, AddSumTcM);
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flopenrc #(4) EMRegAdd3(clk, reset, PipeClearEM, PipeEnableEM, AddSelInvE, AddSelInvM);
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flopenrc #(11) EMRegAdd4(clk, reset, PipeClearEM, PipeEnableEM, AddExpPostSumE, AddExpPostSumM);
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flopenrc #(1) EMRegAdd5(clk, reset, PipeClearEM, PipeEnableEM, AddCorrSignE, AddCorrSignM);
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flopenrc #(1) EMRegAdd6(clk, reset, PipeClearEM, PipeEnableEM, AddOp1NormE, AddOp1NormM);
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flopenrc #(1) EMRegAdd7(clk, reset, PipeClearEM, PipeEnableEM, AddOp2NormE, AddOp2NormM);
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flopenrc #(1) EMRegAdd8(clk, reset, PipeClearEM, PipeEnableEM, AddOpANormE, AddOpANormM);
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flopenrc #(1) EMRegAdd9(clk, reset, PipeClearEM, PipeEnableEM, AddOpBNormE, AddOpBNormM);
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flopenrc #(1) EMRegAdd10(clk, reset, PipeClearEM, PipeEnableEM, AddInvalidE, AddInvalidM);
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flopenrc #(1) EMRegAdd11(clk, reset, PipeClearEM, PipeEnableEM, AddDenormInE, AddDenormInM);
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flopenrc #(1) EMRegAdd12(clk, reset, PipeClearEM, PipeEnableEM, AddConvertE, AddConvertM);
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flopenrc #(1) EMRegAdd13(clk, reset, PipeClearEM, PipeEnableEM, AddSwapE, AddSwapM);
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flopenrc #(1) EMRegAdd14(clk, reset, PipeClearEM, PipeEnableEM, AddNormOvflowE, AddNormOvflowM);
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flopenrc #(1) EMRegAdd15(clk, reset, PipeClearEM, PipeEnableEM, AddSignAE, AddSignAM);
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flopenrc #(64) EMRegAdd16(clk, reset, PipeClearEM, PipeEnableEM, AddFloat1E, AddFloat1M);
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flopenrc #(64) EMRegAdd17(clk, reset, PipeClearEM, PipeEnableEM, AddFloat2E, AddFloat2M);
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flopenrc #(12) EMRegAdd18(clk, reset, PipeClearEM, PipeEnableEM, AddExp1DenormE, AddExp1DenormM);
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flopenrc #(12) EMRegAdd19(clk, reset, PipeClearEM, PipeEnableEM, AddExp2DenormE, AddExp2DenormM);
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flopenrc #(11) EMRegAdd20(clk, reset, PipeClearEM, PipeEnableEM, AddExponentE, AddExponentM);
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flopenrc #(3) EMRegAdd23(clk, reset, PipeClearEM, PipeEnableEM, AddRmE, AddRmM);
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flopenrc #(4) EMRegAdd24(clk, reset, PipeClearEM, PipeEnableEM, AddOpTypeE, AddOpTypeM);
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flopenrc #(1) EMRegAdd25(clk, reset, PipeClearEM, PipeEnableEM, AddPE, AddPM);
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flopenrc #(1) EMRegAdd26(clk, reset, PipeClearEM, PipeEnableEM, AddOvEnE, AddOvEnM);
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flopenrc #(1) EMRegAdd27(clk, reset, PipeClearEM, PipeEnableEM, AddUnEnE, AddUnEnM);
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//*****************
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// fpcmp E/M pipe registers
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//*****************
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flopenrc #(8) EMRegCmp1(clk, reset, PipeClearEM, PipeEnableEM, WE, WM);
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flopenrc #(8) EMRegCmp2(clk, reset, PipeClearEM, PipeEnableEM, XE, XM);
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flopenrc #(1) EMRegcmp3(clk, reset, PipeClearEM, PipeEnableEM, ANaNE, ANaNM);
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flopenrc #(1) EMRegCmp4(clk, reset, PipeClearEM, PipeEnableEM, BNaNE, BNaNM);
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flopenrc #(1) EMRegCmp5(clk, reset, PipeClearEM, PipeEnableEM, AzeroE, AzeroM);
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flopenrc #(1) EMRegCmp6(clk, reset, PipeClearEM, PipeEnableEM, BzeroE, BzeroM);
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// put this in for the event we want to delay fsgn - will otherwise bypass
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//*****************
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// fpsgn E/M pipe registers
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//*****************
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flopenrc #(64) EMRegSgn2(clk, reset, PipeClearEM, PipeEnableEM, SgnResultE, SgnResultM);
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flopenrc #(5) EMRegSgn3(clk, reset, PipeClearEM, PipeEnableEM, SgnFlagsE, SgnFlagsM);
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//*****************
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// other E/M pipe registers
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//*****************
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flopenrc #(1) EMReg1(clk, reset, PipeClearEM, PipeEnableEM, FWriteEnE, FWriteEnM);
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flopenrc #(3) EMReg2(clk, reset, PipeClearEM, PipeEnableEM, FResultSelE, FResultSelM);
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flopenrc #(3) EMReg3(clk, reset, PipeClearEM, PipeEnableEM, FrmE, FrmM);
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flopenrc #(1) EMReg4(clk, reset, PipeClearEM, PipeEnableEM, FmtE, FmtM);
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flopenrc #(5) EMReg5(clk, reset, PipeClearEM, PipeEnableEM, RdE, RdM);
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flopenrc #(4) EMReg6(clk, reset, PipeClearEM, PipeEnableEM, FOpCtrlE, FOpCtrlM);
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flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
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flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
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flopenrc #(1) EMReg9(clk, reset, PipeClearEM, PipeEnableEM, SelLoadInputE, SelLoadInputM);
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//*****************
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// fpuclassify E/M pipe registers
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//*****************
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flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
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//BEGIN MEMORY STAGE
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assign FWriteDataM = FmtM ? FInput1M[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FInput1M[63:32]};
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//adjecent adress values are sent to the FPU, select the correct one
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// -imm is 80000 most of the time vs the error one which is 00000
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// mux3 #(64) FLoadResultMux({HRDATA[31:0], {64-`AHBW+(`XLEN-32){1'b0}}}, {HRDATA[`AHBW-1:`AHBW-32], {64-`AHBW+(`XLEN-32){1'b0}}}, {HRDATA, {64-`AHBW{1'b0}}}, {FmtM, SelLoadInputM}, FLoadResultM);
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// mux2 #(64) FLoadStoreResultMux(FLoadResultM, FInput1M, |FOpCtrlM[2:1], FLoadStoreResultM);
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fma2 fma2(.X(FInput1M), .Y(FInput2M), .Z(FInput3M), .FOpCtrlM(FOpCtrlM[2:0]), .*);
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// second instance of two-stage floating-point add/cvt unit
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fpuaddcvt2 fpadd2 (.*);
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// second instance of two-stage floating-point comparator
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fpucmp2 fpcmp2 (.Invalid(CmpInvalidM), .FCC(CmpFCCM), .ANaN(ANaNM), .BNaN(BNaNM), .Azero(AzeroM),
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.Bzero(BzeroM), .w(WM), .x(XM), .Sel({1'b0, FmtM}), .op1(FInput1M), .op2(FInput2M), .*);
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// Align SrcA to MSB when single precicion
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mux2 #(64) SrcAMux({SrcAM[31:0], 32'b0}, {{64-`XLEN{1'b0}}, SrcAM}, FmtM, AlignedSrcAM);
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//*****************
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//fpregfile M/W pipe registers
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//*****************
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flopenrc #(64) MWFpReg1(clk, reset, PipeClearMW, PipeEnableMW, FInput1M, FInput1W);
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//*****************
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// fma M/W pipe registers
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//*****************
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flopenrc #(64) MWRegFma1(clk, reset, PipeClearMW, PipeEnableMW, FmaResultM, FmaResultW);
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flopenrc #(5) MWRegFma2(clk, reset, PipeClearMW, PipeEnableMW, FmaFlagsM, FmaFlagsW);
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//*****************
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// fpdiv M/W pipe registers
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//*****************
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flopenrc #(64) MWRegDiv1(clk, reset, PipeClearMW, PipeEnableMW, FDivResultM, FDivResultW);
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flopenrc #(5) MWRegDiv2(clk, reset, PipeClearMW, PipeEnableMW, FDivFlagsM, FDivFlagsW);
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flopenrc #(1) MWRegDiv3(clk, reset, PipeClearMW, PipeEnableMW, DivDenormM, DivDenormW);
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//*****************
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// fpadd M/W pipe registers
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//*****************
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flopenrc #(64) MWRegAdd1(clk, reset, PipeClearMW, PipeEnableMW, FAddResultM, FAddResultW);
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flopenrc #(5) MWRegAdd2(clk, reset, PipeClearMW, PipeEnableMW, FAddFlagsM, FAddFlagsW);
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//*****************
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// fpcmp M/W pipe registers
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//*****************
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flopenrc #(1) MWRegCmp1(clk, reset, PipeClearMW, PipeEnableMW, CmpInvalidM, CmpInvalidW);
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flopenrc #(2) MWRegCmp2(clk, reset, PipeClearMW, PipeEnableMW, CmpFCCM, CmpFCCW);
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flopenrc #(64) MWRegCmp3(clk, reset, PipeClearMW, PipeEnableMW, FCmpResultM, FCmpResultW);
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//*****************
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// fpsgn M/W pipe registers
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//*****************
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flopenrc #(64) MWRegSgn1(clk, reset, PipeClearMW, PipeEnableMW, SgnResultM, SgnResultW);
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flopenrc #(5) MWRegSgn2(clk, reset, PipeClearMW, PipeEnableMW, SgnFlagsM, SgnFlagsW);
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//*****************
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// other M/W pipe registers
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//*****************
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flopenrc #(1) MWReg1(clk, reset, PipeClearMW, PipeEnableMW, FWriteEnM, FWriteEnW);
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flopenrc #(3) MWReg2(clk, reset, PipeClearMW, PipeEnableMW, FResultSelM, FResultSelW);
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flopenrc #(1) MWReg3(clk, reset, PipeClearMW, PipeEnableMW, FmtM, FmtW);
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flopenrc #(5) MWReg4(clk, reset, PipeClearMW, PipeEnableMW, RdM, RdW);
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flopenrc #(64) MWReg5(clk, reset, PipeClearMW, PipeEnableMW, AlignedSrcAM, SrcAW);
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// flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FLoadStoreResultM, FLoadStoreResultW);
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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flopenrc #(4) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, FOpCtrlM, FOpCtrlW);
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//*****************
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// fpuclassify M/W pipe registers
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//*****************
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flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
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//#########################################
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// BEGIN WRITEBACK STAGE
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//#########################################
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// mux3 #(64) FLoadResultMux({ReadD[31:0], {64-`AHBW+(`XLEN-32){1'b0}}}, {HRDATA[`AHBW-1:`AHBW-32], {64-`AHBW+(`XLEN-32){1'b0}}}, {HRDATA, {64-`AHBW{1'b0}}}, {FmtM, SelLoadInputM}, FLoadResultM);
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// mux2 #(64) FLoadStoreResultMux(FLoadResultM, FInput1M, |FOpCtrlM[2:1], FLoadStoreResultM);
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//***RV32D needs to give two bus transactions
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mux2 #(64) FLoadResultMux({ReadDataW[31:0], {32{1'b0}}}, {ReadDataW, {64-`XLEN{1'b0}}}, FmtW, FLoadResultW);
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mux2 #(64) FLoadStoreResultMux(FLoadResultW, FInput1W, |FOpCtrlW[2:1], FLoadStoreResultW);
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always_comb begin
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case (FResultSelW)
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// div/sqrt
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3'b000 : FPUFlagsW = FDivFlagsW;
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// cmp
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3'b001 : FPUFlagsW = {CmpInvalidW, 4'b0};
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//fma/mult
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3'b010 : FPUFlagsW = FmaFlagsW;
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// sgn inj
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3'b011 : FPUFlagsW = SgnFlagsW;
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// add/sub/cnvt
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3'b100 : FPUFlagsW = FAddFlagsW;
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// classify
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3'b101 : FPUFlagsW = 5'b0;
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// output SrcAW
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3'b110 : FPUFlagsW = 5'b0;
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// output FRD1
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3'b111 : FPUFlagsW = 5'b0;
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default : FPUFlagsW = 5'bxxxxx;
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endcase
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end
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always_comb begin
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case (FResultSelW)
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// div/sqrt
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3'b000 : FPUResult64W = FDivResultW;
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// cmp
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3'b001 : FPUResult64W = FCmpResultW;
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//fma/mult
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3'b010 : FPUResult64W = FmaResultW;
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// sgn inj
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3'b011 : FPUResult64W = SgnResultW;
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// add/sub/cnvt
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3'b100 : FPUResult64W = FAddResultW;
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// classify
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3'b101 : FPUResult64W = ClassResultW;
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// output SrcAW
|
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3'b110 : FPUResult64W = SrcAW;
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// Load/Store/Move to FP-register
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3'b111 : FPUResult64W = FLoadStoreResultW;
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default : FPUResult64W = {64{1'bx}};
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endcase
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end // always_comb
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|
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// interface between XLEN size datapath and double-precision sized
|
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// floating-point results
|
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//
|
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// define offsets for LSB zero extension or truncation
|
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always_comb begin
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// zero extension
|
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FPUResultW = FmtW ? FPUResult64W[63:64-`XLEN] : {{`XLEN-32{1'b0}}, FPUResult64W[63:32]};
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SetFflagsM = FPUFlagsW;
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end
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endmodule // fpu
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