Ross Thompson
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ebdac1a9d0
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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2457448e29
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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cturek
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f57211bb49
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Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs
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2022-12-10 21:56:35 +00:00 |
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Kip Macsai-Goren
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f486a763d9
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Addded fix for 32 bit periph test and added test to regression
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2022-12-06 09:56:08 -08:00 |
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Kip Macsai-Goren
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2dfa426e10
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added passing GPIO test to 64 bit tests
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2022-12-05 21:31:00 -08:00 |
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Kip Macsai-Goren
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c6c0ef05db
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commented out periph test from wally32 periph so rv32ic doesn't hang
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2022-12-05 20:23:16 -08:00 |
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Kip Macsai-Goren
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ae32e2a9ee
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added passing tests to regression
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2022-12-05 20:16:02 -08:00 |
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Kip Macsai-Goren
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282d06b45f
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added -01 to all WALLY tests
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2022-12-05 20:16:02 -08:00 |
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Ross Thompson
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128b3d20e7
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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Ross Thompson
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de99663b97
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Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider."
This reverts commit 70b89e5214.
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2022-12-04 00:01:58 +00:00 |
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cturek
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70b89e5214
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Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.
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2022-12-02 21:44:29 +00:00 |
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David Harris
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9c1b7e53e4
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FPU divider working with execute stage stall
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2022-12-02 11:11:53 -08:00 |
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David Harris
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4c6003d9e2
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update test list
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2022-12-02 04:28:47 -08:00 |
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David Harris
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ed39099405
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reorder tests
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2022-12-01 16:27:33 -08:00 |
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David Harris
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f64c0589fe
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FPU test list
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2022-12-01 10:18:36 -08:00 |
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Ross Thompson
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bfd238a4fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-11-30 13:30:37 -06:00 |
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Ross Thompson
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5e5cca6ae1
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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ac3e02692b
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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8692ccbafb
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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cturek
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e28a6901a9
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div tests in sim-wally
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2022-11-30 02:32:04 +00:00 |
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Kip Macsai-Goren
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26b4147f40
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added failing satp invalid tests to regression
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2022-11-29 10:43:38 -08:00 |
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cturek
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3fbccbf119
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Updated testbench/wave for fdivsqrt new start signals
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2022-11-22 22:22:26 +00:00 |
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cturek
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d5c5450f8d
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Reoredered tests for arch32m
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2022-11-09 18:42:00 +00:00 |
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cturek
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333da5c945
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Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
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2022-11-06 22:08:18 +00:00 |
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David Harris
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c78643f4e4
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Reorder embench tests to prevent crash
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2022-11-04 15:21:51 -07:00 |
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Ross Thompson
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ae7a71c0f4
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Created one off test to replicate the floating point forwarding hazard bug.
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2022-10-22 16:29:12 -05:00 |
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Kip Macsai-Goren
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d5cd67cf09
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fixed endianness mstatush problem, passes make, not regression
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2022-10-04 17:37:39 +00:00 |
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David Harris
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fce927810a
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Fixed testbench-fp to support all again
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2022-09-21 13:19:48 -07:00 |
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David Harris
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3b0714b059
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-21 10:35:11 -07:00 |
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David Harris
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1c8581dd6d
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Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest
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2022-09-21 10:35:08 -07:00 |
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Ross Thompson
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91fcca9d17
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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David Harris
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8647de5ee4
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make QmM size b+1 indpenedent of radix
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2022-09-20 03:25:09 -07:00 |
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David Harris
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1e6bd26bb6
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Removed EarlyTermShift from fdiv
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2022-09-19 08:44:23 -07:00 |
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David Harris
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198a134304
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FP testbench
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2022-09-18 21:27:21 -07:00 |
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David Harris
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1187187a5c
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Divide testfloat starts with half-precision tests
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2022-09-18 06:46:47 -07:00 |
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Kip Macsai-Goren
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a4fc5d3476
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Created initial endianness tests
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2022-09-16 01:06:26 +00:00 |
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Ross Thompson
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40e7d2648f
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Renamed signals in the LSU.
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2022-09-13 11:47:39 -05:00 |
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David Harris
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c2f81e309b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 11:11:39 -07:00 |
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David Harris
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b0cf73d19c
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Running 16-bit square root cases first in testfloat
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2022-09-07 11:11:35 -07:00 |
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Ross Thompson
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fd4b382ec6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-09-07 12:26:50 -05:00 |
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David Harris
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e01b03e9b2
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Run 16-bit fsqrt tests first
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2022-09-07 10:26:09 -07:00 |
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Ross Thompson
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6581490f9c
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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DTowersM
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dedfadbb14
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-31 00:18:04 +00:00 |
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DTowersM
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f9cbc9cf8e
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fixed qrduino keyerror in embench test
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2022-08-31 00:17:58 +00:00 |
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David Harris
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5956fbdd62
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Fixed checking termination in testfloat testbench
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2022-08-30 10:55:21 -07:00 |
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David Harris
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b4cb9a678a
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renamed srt to fdivsqrt
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2022-08-29 04:04:05 -07:00 |
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David Harris
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921a49921b
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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6409548c8b
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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906f6f2990
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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109bcd470e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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